Error correction encoding and decoding system

ABSTRACT

A rectangular array of 6×150 bits is divided into 50 rectangular arrays of 8×3 bits with 2 check bits added, resulting in 50 codes C 2 . This encoding is executed 50 times to form a rectangular array of 8×150 bits and each of its rows is encoded into a code C 1  of 166 bits with 16 check bits added. This encoding is executed eight times to form a codeword of a generalized product code, which includes 8×166 bits and each row following 12 synchronizing bits. Errors are detected in the codes C 1  decoded from the codeword to produce erasure information which is utilized to correct the code C 2 . Then, the original array is reproduced.

This is a continuation-in-part of abandoned U.S. patent application Ser.No. 3,941, filed Jan. 16, 1979.

BACKGROUND OF THE INVENTION

This invention relates to an encoding and decoding system for digitalinformation having a two-dimensional array of bits and more particularlyto an encoding and decoding system including error correcting means tocorrect errors occurring during the transmission, or recording andreproducing.

In order to correct the burst errors, there have been already knownproduct codes and concatenated codes. The product codes have beenunsuitable for increasing the error correcting capability of encodingand decoding systems as will be described hereinafter while the use ofconcatenated codes has resulted in extremely complicated hardware of thecalculation circuits involved as will be also described later.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a newand improved encoding and decoding system for digital information withan increased error-correcting capability.

It is another object of the present invention to provide a new andimproved encoding and decoding system for digital information includinghardware formed of a small number of components thereof.

The present invention relates to an encoding and decoding system fordigital information having a two-dimensional array of bits including k₁bits disposed in a first direction or a horizontal direction and k₂ bitsdisposed in a second direction orthogonal to the first direction or avertical direction. In order to encode the two-dimensional orrectangular array of k₂ ×k₁ bits, the latter is first divided into frectangular arrays each including b bits in the first direction where bis equal to k₁ divided by f which is an integer. The rectangular arrayincluding k₂ ×b bits is regarded as k₂ information symbols including bbits. Those k₂ information symbols are added with m₂ check symbols inaccordance with a predetermined encoding algorithm to be encoded into n₂symbols whereby a (n₂, k₂) code C₂ over a Galois field GF(2^(b)) areformed. The process as described above is executed f times.

Then, assuming that f symbols each including b bits are again regardedas k₁ bits, predetermined m₁ check bits are added to the k₁ bits in thehorizontal direction and then encoded into a symbol including n₁ bitswhereby a (n₁, k₁) code C, over a Galois field GF(2) is formed. Theprocess as described above is executed n₂ times. Codes C_(Z) thus formedare generalized product codes and are also called (n₁ n₂, k₁ k₂) codesover the Galois field GF(2).

By selecting the parameter for the (n₂, k₂) codes C₂ over the Galoisfield GF(2^(b)) so as to hold n₂ ≦2^(b) +1, it is possible to use amaximum distance separable (which may be abbreviated to MDS") code asthe code C₂.

As a result, the generalized product code can be identical in capabilityto the concatenated code and makes it possible to form encoders anddecoders having less hardware than that required for the concatenatedcode. Furthermore, it will be apparent that the generalized product codeis superior in error correcting capability to the concatenated.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more readily apparent from thefollowing detailed description, taken in conjunction with theaccompanying drawings, in which:

FIG. 1 is a diagram of burst errors occurring in digital informationhaving a rectangular array of bits in which the present invention isdirected towards;

FIG. 2 is a diagram of a codeword of a product code well known in theart;

FIG. 3 is a diagram similar to FIG. 2 but illustrating a codeword of aconcatenated code also well known in the art;

FIG. 4 is a diagram similar to FIG. 2 but illustrating a codeword of ageneralized product code used with the present invention;

FIGS. 5A, 5B and 5C are diagrams illustrating an encoding process forthe generalized product code executed by the present invention;

FIGS. 6A and 6B in combination are a block diagram of one embodiment ofthe present invention applied to a PCM recording and reproducingapparatus;

FIG. 6C is the arrangement of FIGS. 6A and 6B;

FIG. 7 is a block diagram of the k₂ ×k₁ information matrix formingcircuit shown in FIG. 6A;

FIG. 8 is a timing chart illustrating timing signals applied to thearrangement shown in FIG. 7;

FIG. 9A is a schematic diagram illustrating a bit array forming a memorymatrix stored in the RAM device shown in FIG. 7;

FIG. 9B is a diagram similar to FIG. 9A but illustrating a sequence inwhich data is written into the RAM device shown in FIG. 7;

FIG. 9C is a diagram similar to FIG. 9A but illustrating a sequence inwhich data is read out from the RAM device shown in FIG. 7;

FIG. 10 is a block diagram of the encoding adapting circuit for codes C₂shown in FIG. 6A;

FIGS. 11A and 11B in combination are a block diagram of the C₂ and C₁encoders shown in FIG. 6A;

FIG. 11C is the arrangement of FIGS. 11A and 11B;

FIG. 12 is a timing chart illustrating timing signals applied to thearrangements shown in FIGS. 10 and 11;

FIG. 13 is a table illustrating binary numbers corresponding to elementsof a Galois field GF(2³);

FIG. 14 is a block diagram of a multiplier over the Galois field GF(2³)formed of a ROM device and a table illustrating addresses of the ROMdevice and data stored thereat;

FIG. 15 is a block diagram of the C₁ decoder shown in FIG. 6B;

FIG. 16 is a block diagram of the received word forming circuit forcodes C₂ shown in FIG. 6B;

FIG. 17 is a block diagram of the erasure weight and locationcalculation circuits shown in FIG. 6B;

FIG. 18 is a table illustrating inputs to and outputs from the erasurelocation calculation circuit shown in FIG. 17;

FIG. 19 is a block diagram of the erasure location calculation circuitshown in FIG. 17 and formed of gate circuits;

FIG. 20 is a block diagram of one of the gate circuits shown in FIG. 19;

FIGS. 21A and 21B in combination is a block diagram of the C₂ decodershown in FIG. 6B;

FIG. 21C is the arrangement of FIGS. 21A and 21B;

FIG. 22 is a timing chart illustrating timing signals applied to thearrangement shown in FIGS. 15, 16, 17, 21A and 21B;

FIG. 23 is a block diagram of the k₂ ×k₁ information matrix reproducingcircuit shown in FIG. 6B;

FIG. 24A is a schematic diagram illustrating a sequence in which data iswritten into each of the RAM devices shown in FIG. 23;

FIG. 24B is a schematic diagram illustrating a sequence in which data isread out from each of the RAM devices shown in FIG. 23; and

FIG. 25 is a timing chart of illustrating timing signals applied to thearrangement shown in FIG. 23.

DESCRIPTION OF THE PREFERRED EMBODIMENT

For a better understanding of the nature of the present invention,conventional codes used in encoding and decoding systems will now bedescribed. As shown in FIG. 1, burst errors may occur in the horizontaldirection. Also those burst errors occur randomly in the verticaldirection. Such errors occur sometimes in parallel channels ormultitrack tape recording systems upon dropout. The present inventioncontemplates the correction of burst errors such as those shown in FIG.1.

Among error correcting codes of the type having a rectangular array ofbits, there have been already known product codes and concatenatedcodes. In a codeword of a product code shown in FIG. 2, original bitinformation is located in an upper and lefthand rectangular section asviewed in FIG. 2 including k₁₂ rows and k₁₁ columns. Thus originalinformation bits are arranged in a two-dimensional arrangement or arectangular array having the k₁₂ rows and k₁₁ columns. Then apredetermined number m₁₁ of check bits is added to the bits in each rowin the horizontal direction shown at the arrow A in FIG. 1 to form acode C₁₁ while a predetermined number m₁₂ of check bits is added to thebits in each column in the vertical direction shown at the arrow B inFIG. 1 to form a code C₁₂. The code C₁₁ forms a binary (n₁₁, k₁₁) codewherein n₁₁ =k₁₁ +m₁₁ and the code C₁₂ also forms a binary (n₁₂, k.sub.12) code where n₁₂ =k₁₂ +m₁₂. Therefore a product code C_(x) is shown asbeing formed of the code C₁₁ called a row code and the code C₁₂ called acolumn code and form a (n₁₁ n₁₂, k₁₁ k₁₂) code over a Galois fieldGF(2).

In order to correct a burst pattern such as shown in FIG. 1 by using theproduct code, it is assumed that the code C₁₁ is formed of a burst errorcorrecting binary (n₁₁, k₁₁) code and can correct a single burst errorhaving a length of not greater than l₁₁. It is also assumed that thecode C₁₂ is formed of a random error correcting binary (n₁₂, k₁₂) codeand can correct any combination of error bits whose number is notgreater than t₁₂.

With the error pattern of FIG. 1 including U₁₂ burst errors, it isassumed that U₁₂.sup.(0) and U₁₂.sup.(1) burst errors have their lengthswhich are not longer than l and not shorter than l₁₁ +1 whereU₁₂.sup.(1) =U₁₂ -U₁₂.sup.(0). Under the assumed conditions, the productcode C_(x) can correct the error pattern as long as U₁₂.sup.(1) ≦t₁₂.

In a codeword of a concatenated code shown in FIG. 3, originalinformation bits are arranged in a rectangular array located in an upperand lefthand section as viewed in FIG. 3 including k₂₂ rows and k₂₁columns as in the array of FIG. 2. However, original digital informationincluding k₂₂ ×k₂₁ bits are first regarded as informations symbols eachincluding k₂₂ information bits.

Those k₂₂ information symbols are added with m₂₂ check symbolsrespectively and encoded into n₂₂ symbols according to a predeterminedencoding algorithm whereby (n₂₂, k₂₂) codes C₂₂ over a Galois fieldGF(2^(k).sbsp.21) are formed. Then every k₂₁ bits of each symbol areadded with m₂₁ check bits and encoded into (n₂₁, k₂₁) codes C₂₁ over aGalois field GF(2) according to a predetermined encoding algorithm witheach of the codes C₂₁ including n₂₁ bits. The code C₂₂ and the codes C₂₁are called "outer codes" and "inner codes" respectively. The codes C₂₁and C₂₂ form a concatenated code C_(y) that is a (n₂₁ n₂₂, k₂₁ k₂₂) codeover the Galois field GF(2).

Where the concatenated code C_(y) is used to correct an error patternsuch as shown in FIG. 1, it is assumed that the code C₂₁ is formed of aburst error correcting binary (n₂₁, k₂₁) code over the Galois fieldGF(2) and can correct a single burst error having a length which is notlonger than l₂₁. It is also assumed that the code C₂₂ is formed of arandom error correcting binary (n₂₂, k₂₂) code over the Galois fieldGF(2^(k).sbsp.21) and can correct any combination of error symbolshaving a number which is not greater than t₂₂. Furthermore, it isassumed that a maximum distance separable code is used as the code C₂₂.

Where the error pattern, such as that shown in FIG. 1, includes U₂₂burst errors, it is assumed that U₂₂.sup.(0) burst errors have lengthswhich are not longer than l₂₁ and U₂₂.sup.(1) burst errors have lengthswhich are not shorter than l₂₁ +1 where U₂₂.sup.(1) =U₂₂ -U₂₂.sup.(0).Under the assumed conditions, the concatenated code C_(y) can correctsuch an error pattern as long as U₂₂.sup.(1) ≦t₂₂.

The outer code C₂₂ of the concatenated code C_(y) is defined over theGalois field GF(2^(k).sbsp.21) and therefore an encoder and a decodertherefor is required to be operatively associated with calculationcircuits operative over the Galois field GF(2^(k).sbsp.21). As a result,an increase in 2^(k).sbsp.21 causes the hardware of the calculationcircuits to be too complicated to be realized. On the other hand, if k₂₁decreases in value, then a code rate and therefore its efficiency isdecreased. Assuming that the number of the check bits included in thecode C₂₁ or m₂₁ =n₂₁ -k₂₁ decreases as the k₂₁ reduces, the code rate isnot decreased but the code C₂₁ has its capability to correct or detecterrors reduced.

On the other hand, the column code C₁₂ in the product code C_(x) isformed of a binary code. The column code C₁₂ has a code rate of k₁₂ /n₁₂less than that expressed by k₂₂ /n₂₂ of the outer code C₂₂ of theconcatenated code resulting in a decrease in efficiency, on theassumption that row codes of the product code are identical incapability to inner codes of the concatenated code and that the columncode of the product code has the same minimum distance as that of theconcatenated code. This is because the binary code has its capabilitylimited by the Varsharmov-Gilbert bound and because the maximum distanceseparable code used as the outer code C₂₂ of the concatenated code cannot be used as the column code C₁₂ of the product code.

From the foregoing it is seen that the product code has a capability forcorrecting errors which are unsuitable for solving the problems in whichthe present invention is directed while the use of the concatenated codecauses the hardware of associated calculation circuits to be much toocomplicated, as described above.

CONSTRUCTION OF GENERALIZED CODE

Referring now to FIG. 4, there is illustrated a codeword of a uniquecode used with the present invention and called a "generalized productcode" which is abbreviated hereinafter as "G.P. code". The G.P. code iscomposed of (n₁, k₁) codes C₁ over the Galois field GF(2) and (n₂, k₂)codes C₂ over a Galois field GF(2^(b)). Original information is shown inthe upper and lefthand section as viewed in FIG. 4 as having arectangular array of bits including k₁₂ rows and k₁₁ columns.

The encoding process according to the present invention will now bedescribed in conjunction with FIGS. 5A, 5B and 5C, wherein there isillustrated an encoding process executed by the present invention. Asshown in FIG. 5A, a rectangular array of k₂ ×k₁ bits forming originalinformation is divided in a column direction into f rectangular arrayseach including k₂ ×b bits where b=k₁ /f.

In each of the divided rectangular arrays, a rectangular array of 1×bbits is regarded as a symbol corresponding to the element of the Galoisfield GF(2^(b)) and k₂ symbols for the Galois field GF(2^(b)) areencoded into n₂ symbols of the GF(2^(b)) according to a predeterminedencoding algorithm for a code C₂ over GF(2^(b)) after having been addedto m₂ check symbols over GF(2^(b)), where m₂ =n₂ -k₂. This results inthe formation of a rectangular array including n₂ ×b bits.

After the encoding process as described above has been executed f times,a rectangular array including n₂ ×k₁ bits as shown in FIG. 5B.

Subsequently the encoding is effected in the row direction with every k₁bits. More specifically k₁ bits in each row are added to m₁ check bitsand encoded into n₁ bits according to a predetermined encoding algorithmfor a code C₁ over the Galois field GF(2), where m₁ =n₁ -k₁.

After this encoding process has executed n₂ times, a rectangular arrayincluding n₂ ×n₁ bits is formed as shown in FIG. 5C. That rectangulararray results in a codeword of a G.P. code C_(Z) such as shown in FIG. 4forming a binary (n₁ n₂, k₁ k₂) code.

CAPABILITY OF G.P. CODE

The capability of the G.P. code thus formed will now be described.Assuming that the codes, C₁ and C₂ have minimum distances of d₁ and d₂respectively, the G.P. code has a minimum distance of d₁ d₂. However,how the capability of the G.P. code is usefully used is generallydependent upon (1) the selection of the codes C₁ and C₂, (2) thecorrespondence of the configuration of a channel involved to thestructure of the G.P. code, (3) the status of errors occurring in thechannel and (4) the construction and complexity of the decoder involved.Only for purposes of explanation, the present invention will now bedescribed as based on the following assumptions:

(1) A burst error correcting or detecting code is used as the code C₁and a random error-correcting code is used as the code C₂ ;

(2) It is assumed that parallel channels are used whose number n₂ isequal to the code length of the code C₂.

(3) It is supposed that an error pattern includes burst errors developedin the horizontal direction but located randomly in the verticaldirection as shown in FIG. 1; and

(4) The code C₁ is first decoded and then the code C₂ is decoded.

However it is to be understood that the present invention is equallyapplicable to conditions other than those described above.

Also it is assumed that the code C₁ can correct a single burst errorhaving a length which is not longer than l₁ and that the code C₂ cancorrect any combination of error symbols whose number is not greaterthan t₂. Further it is assumed that the error pattern such as shown inFIG. 1 includes U₂ burst errors, and that among them U₂.sup.(0) bursterrors have lengths which are not longer than l₁ and U₂.sup.(1) bursterrors have lengths which are not shorter than l₁ +1 where U₂.sup.(1)=U₂ -U₁.sup.(0). At that time, the G.P. code C_(Z) can correct thoseburst errors as long as U₂.sup.(1) ≦t₂.

DECODING OF G.P. CODE

In parallel channels, each word of the codeword of the G.P. code in ahorizontal direction is transmitted through an associated channel. Onthe receiver side, the words received through the respective channelsare rearranged back into the rectangular array of bits corresponding tothe codeword of the G.P. code on the transmitter side.

The decoding may be sorted into two types employing a hard decision anda soft decision.

(a) With the hard decision employed, the words in the row directioncorresponding to the codeword of the code C₁ are decoded for eachchannel and simultaneously with all of the n₂ channels when the code C₁has been decoded, a rectangular array of n₂ ×k₁ bits is formed and thenis divided into f rectangular arrays each including n₂ ×b bits. The frectangular arrays are applied to a C₂ decoder where the original k₂ ×binformation bits are reproduced. This reproduction is executed with thef rectangular arrays each including k₂ ×b bits.

In the decoding process as described above, the capability of the G.P.code is secured. That is, the U₂.sup.(1) burst errors having lengthswhich are not shorter than l₁ +1 and the U₂ --U₂.sup.(1) burst errorshaving lengths which are not longer than l₁ have been corrected as longas U₂.sup.(1) ≦t₂.

Upon the occurrence of long burst errors always having lengths which arenot shorter than l₁ +1, the decoding process as described above cancorrect the long burst errors whose number is greater than t₂.

(b) With the soft decision employed, the code C₁ is used as an errordetecting code so that error detected information provided by thedecoding of the code C₁ is used, as erasures, in the process of decodingthe codes C₂. When the code C₂ has been decoded, a C₁ decoder isoperated to detect errors in the row direction. Then, error detectedinformation is stored in an associated register as erasures. Thisinformation indicates which of the words in the row direction has beenerroneous.

When the number s of the erasures is not greater than 2t₂, the value sand error detected location information are entered into a C₂ decoder asan erasure weight and erasure location information respectively.

Upon the occurrence of long burst errors having lengths which are notshorter than l₁ +1 alone, it can be expected that the decoding processas described above can correct, in almost all cases, the long bursterrors whose number is not greater than 2t₂.

In order to compare the G.P. code with the conventional product code, itis assumed that the G.P. code is the same in codes in the horizontaldirection as the product code and that the G.P. code includes (n₂, k₂)codes in the vertical direction using maximum distance separable codeswhere n₂ ≦n^(B) +1. Under the assumed conditions the G.P. code has thecapability expressed by

    d.sub.2 =n.sub.2 -k.sub.2 +1                               (1)

where d₂, n₂ and k₂ are previously defined.

On the other hand, the product code includes binary (n₁₂, k₁₂) codes C₁₂in the column direction and has the capability expressed by

    d.sub.12 =n.sub.12 H.sup.-1 (1-k.sub.12 /n.sub.12)         (2)

where d₁₂ designates a minimum distance of the codes C₁₂ and H⁻¹ (1-k₁₂/n₁₂) designates an inverse function of a binary entropy functionexpressed by

    H(x)=-x log.sub.2 x-(1-x) log.sub.2 (1-x)                  (3)

By comparing the expression (1) with the expression (2), it is seenthat, for n₂ =n₁₂ and k₂ =k₁₂, d₂ is greater than d₁₂ so that the G.P.code is superior in capability to the product code.

Also, in order to compare the G.P. code with the concatenated code, itis assumed that the G.P. code is identical in codes in the horizontaldirection to the concatenated code and that codes C₂ of the G.P. codeare maximum distance separable codes as is the outer code C₂₂ of theconcatenated code. Under the assumed conditions, the G.P. code issubstantially identical in capability to the concatenated code providedthat n₂ ≦2^(b) +1. However, the codes C₂ of the G.P. code are definedover the Galois field GF(2^(B)) whereas the outer codes C₂₂ of theconcatenated code are defined over the Galois field GF(2^(R).sbsp.21).This means that the former requires a calculation circuit operative overthe Galois field GF(2^(B)) while the latter requires a calculationcircuit operative over the Galois field GF(2^(K).sbsp.21) or GF(2^(bf)).Therefore, the latter requires the hardware equal to from about f toabout f² times that of the former. It is noted that the use of the G.P.code requires only a control circuit for repeatedly using the samehardware f times. Accordingly, the use of the G.P. code can sharplyreduce the hardware needed as compared with the use of the concatenatedcode.

It is noted that, where n₂ ≈2^(k).sbsp.1 +1, the G.P. code is identicalto the concatenated code because the parameters of the G.P. code holdb=k₁. However, if the system has the parameter n₂ much smaller than2^(k).sbsp.1 +1, then a minimum b can be selected to fulfill n₂ ≦2^(b)+1 as the parameter of the G.P. code. Therefore, it may be said that theuse of the G.P. codes can have the same capability as the use ofconcatenated codes with less hardware required than that required forthe latter. For example, assuming the present invention is practicallyapplied to a PCM multi-track digital recording apparatus having theparameters n₂ of from 8 to 20 and n₁ of from 100 to 300, the sameincludes n₂ parallel channels by considering that record tracks formrespective channels. Under these circumstances, the use of theconcatenated codes requires calculation circuits operative, for example,over the Galois field GF(2¹⁰⁰) resulting in a complicated hardwareconfiguration. On the other hand, the use of the G.P. codes requiresonly calculation circuits operative, for example, over the Galois fieldGF(2⁵). Accordingly, the G.P. codes are sharply advantageous over theconcatenated codes.

IMPLEMENTATION

Referring now to FIGS. 6A and 6B, there is illustrated one embodimentaccording to the encoding and decoding system of the present inventionutilizing the G.P. code C_(z) as shown in FIG. 5 and applied to a PCMmulti-track digital recording apparatus. The arrangement illustratedwill now be described on the assumption that:

(1) a burst error detecting code is used as the code C₁ and a maximumdistance separable code having a minimum distance of 2t₂ +1 is used asthe code C₂ ;

(2) the code C₂ included in the G.P. code has a code length n₂ selectedto be equal to the number of record tracks included in the PCM recordingapparatus;

(3) the error pattern as shown in FIG. 1 is caused. That is, bursterrors occur in the row direction in which an associated record tapetravels and those burst errors are developed randomly in the columndirection or in a direction of width of the tape; and

(4) the G.P. code is decoded so that the codes C₁ are subjected to theerror detection to provide erasure information and the codes C₂ aresubjected to the erasure and error decoding.

The arrangement illustrated in FIG. 6A comprises an input terminal 10 towhich an analog musical signal from a microphone (not shown) is applied;an analog-to-digital converter 12 is connected to the input 10 and anencoder 14 for G.P. codes, which is called hereinafter a "C_(Z)encoder", is connected to the converter 12 and generally designated bythe reference numeral 14. The C_(Z) encoder 14 includes a k₂ ×k₁information matrix forming circuit 16 connected to the analog-to-digitalconverter 12, a C₂ encoding adapting circuit 18 connected to the matrixforming circuit 16, a C₂ encoder 20 connected to the adapting circuit 18and a plurality of C₁ encoders connected to the C₂ encoding adaptingcircuit 18. The number of C₁ encoders 22 is equal to the number oftracks on an associated magnetic record tape 32. The C_(Z) encoder 14further includes a timing signal generator 24 for generating timingsignals required for the components thereof to be operated.

Each of the C₁ encoders 22 is connected via a synchronizing patternadding circuit 26 to an associated modulation circuit of a modulator 28including a plurality of outputs connected to respective magneticrecording heads 30, one for each track of the magnetic record tape 32.The magnetic recording heads 30 record simultaneously the outputs fromthe modulator 28 on the magnetic record tape 32.

The C_(Z) encoder 14 forms a codeword of a G.P. code arranged in arectangular array of n₂ ×n₁ bits such as shown in FIG. 4. The codewordis added with synchronizing patterns by the synchronizing patterngenerator circuits 26. Then the codeword with the synchronizing patternsis modulated into signals suitable for the magnetic recording by themodulator 28 and modulated signals are recorded on associated tracks onthe magnetic record tape 32 by the recording heads 30 respectively.

In the arrangement illustrated in FIG. 6B, a plurality of reproducingheads 34 are operatively coupled to the record tape 32, one for eachrecord track on the latter, to reproduce digital signals from therespective track. Each of the reproducing heads 34 is connected to anassociated circuit of a demodulator 36 where the digital signals aredemodulated. The demodulator 36 includes a plurality of outputs, one foreach track on the tape 32. Those outputs of the demodulator 36 areconnected to respective series combinations of a synchronization patterndetector circuit 38 and a time base corrector 40 which are, in turn,connected to a decoder for G.P. codes C_(Z) (which is called hereinaftera "C_(Z) decoder") generally designated by the reference numeral 42.

The C_(Z) decoder 42 includes a plurality of C₁ decoders connected tothe time base correctors 40 respectively each producing an erasureoutput 46 indicating that an associated code C₁ detects an error orerrors and an information output 48. The erasure output 46 from each C₁decoder 44 is delivered to both an erasure weight calculation circuit 50and an erasure location calculation circuit 52 while the informationoutput 48 therefrom is in the form of a series array of k₁ bitscorresponding to an information portion of the decoded code C₁ resultingfrom an associated track and those k₁ bits are serially delivered to areceived C₁ word forming circuit 54. The erasure weight calculationcircuit 50 includes a plurality of outputs connected to a C₂ decoder 56,one for each track on the tape 32, and the erasure location calculationcircuit 52 includes also a plurality of outputs connected to the C₂decoder 56, one for each track. Similarly the received word formingcircuit of the code C₂ 54 is connected to the C₂ decoder 56. The C₂decoder 56 output is connected to a k₂ ×k₁ information matrixreproducing circuit 60.

The C_(Z) decoder 42 includes a timing signal generator 58 forgenerating timing signals which are applied to the components of theC_(Z) decoder 42.

The k₂ ×k₁ information matrix reproducing circuit 60 is connected to acompensation circuit 62 which is subsequently connected to adigital-to-analog converter 64 which is, in turn connected to an outputterminal 66 serving to apply a reproduced analog music signal to anamplifier having a loudspeaker (not shown).

In operation, the signals recorded on the tracks on the magnetic recordtape 32 are reproduced by the reproducing heads 34 to form a pluralityof signal sequences, one for each track. Each of the synchronizingpattern detector circuits 38 detects the synchronizing pattern includedin the associated signal sequence to provide a received wordcorresponding to the code C₁ resulting from an associated track. Then,each of the time base correctors 40 absorbs and removes a skew or skewsand/or a jitter or jitters from the received word reproduced from theassociated track. In this way, a received word has been reproduced in arectangular array of n₂ ×n₁ bits corresponding to a transmitted codeword.

The received word of n₂ ×n₁ bits is processed in the C_(Z) decoder 42 asfollows:

First, each of the C₁ decoders 44 detects whether or not errors havebeen caused in the received word of n₁ bits corresponding to theassociated code C₁. In the presence of an error, as determined by the C₁decoder 44 the latter applies its erasure output 46 in the form of abinary ONE to both the erasure weight and location calculation circuits50 and 52 respectively. On the other hand, in the absence of an error,as determined by the C₁ decoder 44, the latter applies the erasureoutput 46 in the form of a binary ZERO to the two circuits 50 and 52.

Each of the C₁ decoders 44 also delivers a received k₁ bit word,corresponding to an associated information portion included in thereceived n₁ bit word corresponding to the associated code C₁, to thereceived word-of-code C₂ forming circuit 54 as an information output 48.

All the C₁ decoders 44 perform the operation as described above in aparallel relationship.

The number of tracks including errors, as determined by the C₁ decoders44, are calculated as the number of erasures or erasure weightinformation, by the erasure weight calculation circuit 50 and thendelivered to the C₂ decoder 56 through an associated one of leads 50-0.

Also the erasure location calculation circuit 52 uses the erasureoutputs 46 to transform the serial numbers of the tracks having theerrors occurring thereon the erasure location information in the formrequired to be calculated in the C₂ decoder 56. This information issupplied to the C₂ decoder 56 through leads 52-0.

On the other hand, the received work-of-code C₂ forming circuit 54 isoperated to divide the k₂ bits from each C₁ decoder 44 into b bitsapiece to form rectangular arrays each including n₂ ×b bits and todeliver those arrays to the C₂ decoder 56.

Then, the C₂ decoder 56 corrects the errors for every n₂ ×b bits on thebasis of the received word from the received word-of-code C₂ formingcircuit 54, the erasure weight information from the erasure weightcalculation circuit 50 and the erasure location information from theerasure location calculation circuit 52.

The C₂ decoder 56 executes the correction as described above f timeswhere f=k₁ /b and supplies outputs to the k₂ ×k₁ information matrixreproducing circuit 60 one for every k₂ ×b bits. The k₂ ×k₁ informationmatrix reproducing circuit 60 reproduces a k₂ ×k₁ information matrix andapplied to; the compensation circuit 62, the analog musical signal inthe digital form including the sampled values thereof.

It is assumed that, when the C₁ decoders 44 have decoded received words,s erasures are detected and e errors are undetected. In other words, itis assumed that the erasure weight and location calculation cirduits 50and 52 respectively have entered thereinto information concerning the serasures alone and no information concerning the e undetected errors.Under the assumed conditions, the capability to correct t₂ -ple errorsof the code C₂ can correct the s erasures and the e undetected errors aslong as

    s+2e<2t.sub.2 +1                                           (4).

Also, if the erasure weight calculation circuit 50 calculates an erasureweight of not less than 2t₂ +1 or if erasures are detected on 2t₂ +1 ormore tracks, then no correction is effected while only the detection iseffected and the compensation circuit 62 is operated to effect thecorrection by interpolation by using data in front of and in back ofeach of the erasures. This is because the reliability is prevented fromdecreasing.

Furthermore, the arrangement shown in FIGS. 6A and 6B will now bedescribed in more detail with respect to the following concrete example:

(1) There is used a cyclic redundancy check (which is abbreviated toCRC) code known as one of burst error detecting codes as the code C₁. Agenerator polynomial G(x) is given by

    G(x)=X.sup.16 +X.sup.12 +X.sup.5 +1                        (5)

in accordance with the CCITT V 41. As codes C₂ (8,6) Reed-Solomon codesover the Galois field GF(2³) are used. The code parameters include n₁=166, k₁ =150, n₂ =8 and k₂ =6;

(2) A stationary head, 8-track PCM recording apparatus is considered;

(3) An error pattern caused in an associated magnetic record tapeincludes burst errors with the mean burst length on the order of from100 to 500 occurring in the row direction or a direction of travel ofthe tape and burst errors randomly developed in the column direction ora direction of width of the tape; and

(4) In order to decode the G.P. code, error detected information of theCRC code or code C₁ is utilized as erasure information to decode thecode C₂ to thereby correct errors developed on up to two tracks.

DETAILS OF ENCODING UNIT

FIG. 7 illustrates, in block diagram form, the details of the k₂ ×k₁information matrix forming circuit 16 shown in FIG. 6A. The arrangementillustrated comprises an input terminal 70 to which digital informationfrom the analog-to-digital converter 12 is applied, a pair of first andsecond random access memory devices 72 and 74 (which is each abbreviatedto "RAM"), a pair of first and second selectors 76 and 78 connected tothe first and second RAM devices 72 and 74 respectively and a thirdselector 80 connected to those RAM devices 72 and 74. Each of the firstand second RAM devices 72 and 74 has a storage capacity of 6×178 bitsand is put in the write or read cycle of operation under the control ofthe associated selector 76 or 78 so that the first RAM device 72 is putin the write cycle of operation, while the second RAM device 74 is putin the read cycle of operation and vice versa. Synchronizing patternsand check bits for codes C₁ may be preliminarily stored in each of theRAM devices 72 and 74.

The third selector 80 is connected to a serial in-parallel output type 6bit shift register 82 which transforms inputs serially applied theretoto outputs supplied in parallel to a transfer register 84 in order topermit the output from the third selector 80 to be recorded on theparallel tracks on the magnetic tape. The transfer register 84 is formedof six D type FLIP-FLOP's each connected to an output terminal 86subsequently connected to the C₂ encoding adapting circuit 18 as shownin FIG. 6A.

Developed at an input terminal 88 is block timing signal ER11 indicatinga partition between each pair of adjacent rectangular bit arrays, eachincluding 6×178 bits in the example illustrated. The pulse ER11 issupplied to a T FLIP-FLOP 90 where it is halved in pulse repetitionfrequency. The pulse thus halved in frequency is applied to the secondand third selectors 78 and 80 on the one hand and applied to the firstselector 76 through an inverter 92 on the other hand.

The write address forming circuit 94, including a counter and a counterdecoder, responds to pulses ER130 to form write addresses, although thecounter and counter are not illustrated. The read address formingcircuit 96 similarly forms read addresses in response to RAM read pulsesER310.

FIG. 8 shows various clock pulses or timing signals required foroperating the essential components of the k₂ ×k₁ matrix forming circuit16 illustrated in FIG. 7.

In FIG. 8, first row shows the block timing signal ER11 as describedabove and a second row shows clock pulses or sampling signals ER12 forsampling musical information having such a predetermined pulserepetition period that 60 pulses are developed for each pulse repetitionperiod of the block timing signal ER11. The sampling signal ER12 may bea conversion signal for the analog-to-digital converter 12. A third rowshows RAM write pulses or signals ER13 which are applied to that RAMdevice 72 or 74 operated in the write cycle. A fourth row shows a trainof reference clock pulses ER130 from which the RAM write pulses ER13 areprepared so that one group of 15 pulses ER13 is developed in each pulserepetition period of the pulses ER12. The reference clock pulses ER130are supplied to the write address forming circuit 94.

A fifth row shows a replica of the frame pulses ER11 and a sixth rowshows bit timing pulses or signals ER22 having such a predeterminedpulse repetition period that 178 timing pulses are developed in onepulse repetition period of the block timing signal ER11.

A seventh row shows the pulses ER22 in the extended time base and aneighth row shows RAM read pulses or signals ER31 applied to that RAMdevice 74 or 72 operated in the read mode, RAM read pulses ER31 beingdeveloped in one pulse repetition period of the bit timing bits ER22. Aninth row show a train of reference clock pulses ER310 from which theRAM read pulses ER31 are prepared. The train of reference clock pulsesER310 is applied to the read address forming circuit 96 and the pulsesER31 are shown in FIG. 7 as being also applied to the shift register 82.

A positive rectangular pulse s1 shown in a tenth row is applied to apoint P (see FIG. 7) or the set input to the first selector 76 while anegative rectangular pulse s2 shown in an eleventh row is applied to apoint Q (see FIG. 7) or the set terminal of the second selector 78.

The lowmost row shows an output O from the third selector 80 developedon a lead e (see FIG. 7).

Referring back to FIG. 7, digital data from the input terminal 70 isentered into that RAM device 72 or 74 selected to be operated in thewrite cycle in response to the RAM write pulses ER13 and written atwrite addresses directed by the write address forming circuit 94resulting in data being arranged as shown in FIG. 9A. The writeaddresses are alloted to 6×150 bit positions, one for each bit position,and for every particular sampling frequency e.g.-50.4 Khz, so that eachgroup of 15 sampled bits are written at 15 bit positions continuouslyarranged in the row direction.

As shown in FIG. 9A, each RAM device 72 or 74 includes 6×12 and 6×16 bitpositions disposed on the lefthand and righthand end portionsrespectively and an intermediate bit portion partitioned into tensections, each including 15 columns. Both end portions are hatched andreserved for synchronizing patterns and check bits without informationbits written therein because the timing pulses or signals can readily beprepared. The sampled information bits are written in the intermediateportion so that the 15 sampled bits forming the first row aresuccessively written in the first section in the first row designated bythe reference numeral 1 in a circle and then, 15 bits of the secondgroup are successively written in the first section in the second rowdesignated by the reference numeral 2 in a circle and so on until thesixth bit group is written in the first section in the sixth rowdesignated by the reference numeral 6 in a circle.

Then, the writing process as described above is repeated with the secondsection of the intermediate portion and so on. When the last bit groupis written in the last or tenth section in the sixth row designated bythe reference numeral 60 in a circle, the writing process is completed.The bits written in each section in each row are designated by thereference ordinal numerals 1, 2, . . . , 15.

The sequence in which the sampled bits are written in the RAM device isillustrated by the arrow in FIG. 9B. As shown in FIG. 9B, the arrowstarts with the 13th bit position in the first row and reaches the 27thbit position in the same row. Then the arrow is returned back to the13th bit position in the second row and goes to the 27th bit position inthe same row and so on until the arrow reaches the 27th bit position inthe sixth row. Thereafter the arrow depicts a zigzag path as describedabove between the 28th and 42th bit positions in the first through sixthrows and so on.

When one of the RAM devices, for example, the device 72, is operated inthe write cycle, the other RAM device 74 is put in the read cycle ofoperation and read out from read addesses directed by the read addressforming circuit 96 in response to the RAM read pulses ER31 by the thirdselector 80. As described above, the third selector 80 is alwaysoperated to read out the stored bits from that RAM device put in theread cycle of operation. The reading operation starts with a bitposition lying in the first row and first column and goes to a bitposition lying in the sixth row and first column after which the readingoperation is repeated in the column direction with the succeedingcolumns. Finally, the 178th column is read out in the column direction.

The bits read out by the third selector 80 are in the form of separatetrains of six bits O as shown in the last row of FIG. 8. In each pulsetrain, the reference numerals 1, 2, 3, . . . , 60 in the circledesignate serial numbers of samples rows and the reference numerals 1,2, . . . , 15 denoted below the circled reference numerals designate bitposition in each sample.

It is noted that 6 bits designated by the reference numeral 1 follow by6×12 dummy bits (not shown) and those designated by the referencenumerals 60 are followed by 6×16 dummy bits (not shown) for the purposeas will be apparent later.

The trains of six bits O are serially supplied to the register 82 oneafter another and the register 82 provides parallel outputs to thetransfer register 84 and then the output terminals 86 so as todistribute the outputs from the RAM device operated in the read cycle tothe associated tracks on the magnetic tape.

In the reading operation, what is entered into those bit positionsreserved for the synchronizing patterns and check bits is unknown. Suchbit positions are designated by asterisks * in FIG. 9B. Data at the bitpositions designated by asterisks are replaced by proper data in thelater encoding steps.

The C₂ encoding adapting circuit 18 shown in FIG. 6A may be of a circuitconfiguration as shown in FIG. 10. In FIG. 10, each of six inputterminals 102 is adapted to be connected to an associated one of theoutput terminals 86 shown in FIG. 7 and also to a series combination ofone bit delay circuits 104, 106 and 108. Those delay circuits are formedof D FLIP-FLOP's applied with a train of clock pulses ET16 as will bedescribed later. The delay circuits 104 are connected to respectiveoutput terminals 110 and the delay circuits 106 are connected torespective output terminals 112. Similarly the delay circuits 108 areconnected to respective output terminals 114 and also to other outputterminals 116 respectively which are connected to the C₁ encoders 22(see FIG. 6) respectively. Three sets of the output terminals 110, 112and 114 are connected to the C₂ encoder 20 as shown in FIG. 6A.

Data applied to each of the input terminals 102 is delayed in anincremental manner by one bit by the associated delay circuits 104, 106and 108 the and data thus delayed is delivered to the mating outputterminals 110, 112 and 114. More specifically, six bits delivered to theoutput terminals 114 comprise data just preceding the six bits deliveredto the output terminals 112. Also, six bits delivered to the outputterminals 112 comprise data just preceding the six bits delivered to theoutput terminals 110. Furthermore, six bits developed at the outputterminals 116 are delayed by three bits as compared with those six bitsapplied to the input terminals 102.

In this way the data passed through the input terminals 102 can beentered into the C₂ encoder 20 for every three bits.

The C₂ encoder 20 and the C₁ encoder 22 may be of a circuitconfiguration shown in FIG. 11. In the arrangement illustrated, threesets of input terminals 120, 122 and 124 are connected to a first, asecond and a third selector 126, 128 and 130 respectively and alsoadapted to be connected to the three sets of output terminals 110, 112and 114 of the C₂ encoding adapting circuit 18 (see FIG. 10)respectively.

Each of the selectors 126, 128 or 130 selects successively the firstthrough sixth rows or tracks in response to track selecting signals orpulses EG21, EG22, . . . , EG26 successively applied thereto.

Each of those selectors 126, 128 and 130 includes an output connected toone input of an EXCLUSIVE OR gate 132 respectively. The outputs of thethree EXCLUSIVE OR gates 132 are connected to three inputs of a 3 bitmemory circuit 134 formed of three parallel MASTER-SLAVE or M-SFLIP-FLOP's, one for each bit. The memory circuit 134 includes a resetinput R having reset pulses or signals ET21 applied thereto and a clockinput CLK having timing pulses or signals ET22 appled thereto. Thecircuit 134 has three outputs connected to the other inputs of theEXCLUSIVE OR gates 132 and also connected to the three inputs of a 3 bitshift register 136 having timing signals ET23 and ET24 applied thereto.

In FIG. 11B an α_(i) generator circuit 138 is shown as including a resetinput R having the reset signals ET21 applied thereto and a clock inputCLK having the timing signals ET22 applied thereto. The output ofcircuit 138 are connected to a multiplication circuit 140. Themultiplication circuit 140 includes other inputs connected to theoutputs of the selectors 124, 126 and 128. The α_(i) generator circuit138 successively generates patterns α₁, α₂, . . . , α₆ corresponding toelements α_(i) of the Galois field GE(2³) in the order of the elementsarranged in the first row on the righthand side of the expression (6)and the multiplication circuit 140 is operative to multiply informationsymbols a_(i) (a_(i) εGF(2³)) for the code C₂ by the elements α_(i) ofthe Galois field GF(2³). The multiplication circuit 140 is formed of aread only memory device (which is abbreviated as an "ROM") having acapacity of 2⁶ ×3 bits into which the results of the multiplication hasbeen preliminarily written.

The multiplication circuit 140 includes three outputs connected to aseries combination of three parallel EXCLUSIVE OR gates 142, a memorycircuit 144 and a 3 bit shift register 146 identical to the components132, 134 and respectively and interconnected in the same manner as thelatter elements 132, 134 and 136. The shift registers 136 and 146 areconnected to a pair of inputs, of an EXCLUSIVE OR gate 148.

A set of input terminals 150 are adapted to be connected to the outputterminals of the C₂ encoding adapting circuit shown in FIG. 10. Thoseinput terminals 150 are connected to respective C₁ encoders 152 labelledCRC which produce cyclic redundancy check bits and may be commerciallyavailable under the designation. Type 9401 IC from the FairchildSemiconductor Corporation. Each of the C₁ encoders 152 includes a resetinput R and a clock input CLK which receive reset pulses ET11 and clockpulses ET15 respectively and an output connected to one input of an ANDgate whose other input receives check write enable pulses ET13. Each ofthe input terminals 150 is also connected to one input of another ANDgate whose other input receives information write enable pulses EG12.Then, the outputs of the two AND gates are connected to a pair of inputsof an OR gate to form a selector 154. The selector 154 selects either aninformation bit portion or a check bit portion in response to the writeenable signal EG12 or EG13 respectively. The selected bit portion isdelivered to an output terminal 156 connected to the OR gate output.

The shift registor 146 is also connected to a series combination of a C₁encoder 152 and a selector 154 identical to the selector 152 asdescribed above. Also the EXCLUSIVE OR gate 148 includes an outputconnected to a series combination of a C₁ encoder and a selectoridentical to those described above. The last-mentioned two selectors areconnected to different output terminals 156 respectively.

The pulses and signals described in conjunction with FIG. 11 areillustrated in FIG. 12 with associated other timing signals.

In FIG. 12, the first row shows one bit frame and one portion of theadjacent frames after having been coded. As shown, the bit frame isdesignated by the reference characters and numeral ET00 and composed ofa synchronizing pattern including 12 synchronizing bits, digitalinformation including 150 bits, and 16 CRC bits contiguous to oneanother in the named order. Therefore, the bit frame totals 178 bits.

The second row shows a block timing signal ET11 identical to the blocktiming pulses ER11 shown in FIG. 8. The timing signal ET11 is developedat each partition between adjacent rectangular arrays such as shown inFIG. 5 and has a pulse repetition period equal to 178 times the durationthereof. The third row shows a train of 12 write timing pulses ET12 forthe synchronizing pattern including a first pulse rising simultaneouslywith the block timing signal ET11 and is followed by a train of 150write timing pulses ET13, shown in the fourth row, to write informationbits of codes C₁. Then, a train of 16 write timing pulse ET14 for checkbits, shown in the fifth row, follows the pulse train ET13 which isfollowed by the next succeeding timing signal ET11. The sixth row showsa train of 166 pulses ET15 for writing bits included in each frameexcept for the synchronizing pulses, that is to say, codewords of thecode C₁. A pulse train ET16, shown in the seventh row, includes 178 bittiming pulses developed during each frame. The pulse trains ET12 throughET16 have a common pulse repetition period.

The eighth row shows a train of 50 shifting pulses ET17 which is alsoshown in the fifteenth row as a train of 50 shifting pulses ET23. Thepulses ET17 or ET23 are applied to the shift registers 136 and 146 tocause the latter to effect one logic operation with an incremental timedelay corresponding to every three continuous bits.

The ninth row shows a write enable rectangular pulse EG11 for thesynchronizing pattern rising simultaneously with the first pulse of thepulse train ET12 and falling substantially simultaneously with the firstpulse of the pulse train ET13. When the rectangular pulse EG11 is abinary ONE as illustrated, the 12 synchronizing pulses ET12 are enabledto enter a synchronizing pattern into an associated frame. The tenth rowshows a write enable rectangular pulse EG12 for information bits of thecode C₁ rising simultaneously with the fall of the rectangular pulsesEG11. When the rectangular pulse EG12 is a binary ONE, the 150 bit writepulses ET13 are enabled to enter the information bits of the code C₁into the frame after which the pulse EG12 falls. The elevated row showsa write enable rectangular pulse EG13 for the check bits risingsimultaneously with the fall of the pulse EG12 and fallingsimultaneously with the end of each frame. When the pulse EG13 is abinary ONE, the 16 check pulses ET14 are enabled to enter the check bitsfor the code C₁ into the frame. The twelfth row shows a write enablerectangular pulse EG14 for codewords of the code C₁ risingsimultaneously with the fall of the pulse EG11 and falling at the end ofeach frame. When the write enable pulse EG14 is a binary ONE, the 166pulses ET15 are enabled to enter the codewords of the code C₁ including166 bits into the frame.

The thirteenth row shows the pulse train ET21, which is a replica of thepulse train ET13, illustrated in an extended time base and applied tothe memory circuits 134 and 144 and the α_(i) generator circuit 138 (seeFIG. 11) as reset pulses. The fourteenth row shows a pulse train ET22applied to the clock input to the memory circuits 134 and 144 and theα_(i) generator circuit 138 (see FIG. 11). As shown, the pulse trainET22 includes 6 pulses developed at equal time intervals for one pulserepetition period of the bit timing pulses ET13. A pulse train ET23shown in the fifteenth row is a replica of the train of shifting pulsesET17 illustrated in an extended time base. A train of 150 pulses ET24shown in the sixteenth row serves to shift 3 bit check symbols one bitby one bit.

The seventeenth row et seq show trains of 150 track selecting pulsesEG21 through EG26 applied to the selectors 120, 122 and 124 (see FIG.11) to successively select bits on the first through sixth rowscorresponding to the first through sixth tracks on the magnetic tape.Each of the pulse trains has a common pulse repetition period andincludes pulses rising simultaneously with the fall of adjacent pulsesof the just preceding pulse train.

The encoding algorithm effected by the arrangements shown in FIGS. 7, 10and 11 will now be briefly described.

First, 6×150 bit original information is divided or grouped into 50rectangular arrays each including 6×3 bits.

Then, a rectangular array of 1×3 bits is regarded as a symbolcorresponding to the element of the Galois field GE(2³) in the 6×3 bitrectangular array. Two check symbols are added to the 6×3 bitrectangular array in accordance with an encoding algorithm for (8,6)Reed-Solomon codes over the Galois field GF(2³) whereby the rectangulararray is encoded into eight symbols resulting in a rectangular arrayincluding 8×3 bits.

The process as just described is executed 50 times to form a rectangulararray including 8×150 bits.

Subsequently, 16 check bits are added to 150 bit arranged in the rowdirection or the direction of travel of the tracks in accordance with anencoding algorithm for (166, 150) CRC codes over the Galois field GF(2)resulting in the encoding thereof into 166 bits.

After this encoding has been effected eight times, a rectangular arrayof 8×166 bits are made up as a codeword of a G.P. code.

A parity check matrix for the (8,6) Reed-Solomon code over GF(2³) may beexpressed by ##EQU1## where α₁, α₂, . . . , α₆ designate the elements ofGF(2³) except for zero (0) and unity (1) and are given by rearrangingproperly α, α², . . . , α⁶. For example, the elements may be selectedsuch that α₁ =α⁵, α₂ =α⁴, α₃ =α⁶, α₄ =α², α₅ =α³ and α₆ =α. In thiscase, the α_(i) generator circuit 138 shown in FIG. 11 and alsodescribed later may be formed of a down counter.

The element α is the primitive element of GF(2³) and satisfies α³ +α+1=0on the assumption that the calculation is effected over GF(2³).

FIG. 13 illustrates the correspondency of the elements of GF(2³) andcoefficients α², α¹ and α⁰ in the binary form.

Assuming that a₁, a₂, . . . , a₆ designate information symbols of theReed-Solomon code, check symbols a₇ and a₈ may be expressed by ##EQU2##where the calculation is effected over GF(2³).

Referring back to FIG. 11, the arrangement illustrated will now bedescribed in conjunction with the encoding process as described above.The 6×3 bit information is applied to the selectors 126, 128 and 130through the sets of input terminals 120, 122 and 124 respectively, andthose selectors respond to the row selecting pulses EG21, EG22 . . . ,EG26 to pick up three bits successively and in a parallel relationshipfrom the first through sixth rows or tracks. Every 3 bit informationgroup thus selected passes through the EXCLUSIVE OR gates 132 to thememory circuit 134 formed of the three M-S FLIP-FLOP's where thecontinued sum is formed under the control of the pulses ET21 or ET13 andET22. After having been thereby added with the information symbols a₁,a₂, . . . , a₆, the shift register 136 has registered therein ##EQU3##appearing on the righthand side of the expression (8) under the controlof the pulses ET23 and ET24.

The α₁ generator circuit 138 having the pulses ET21 and ET22 appliedthereto successively generates patterns α₁, α₂, . . . , α₆ correspondingto the elements of the Galois field GF(2³) in the order shown in thefirst row of the righthand side of the expression (6). This generationof the patterns can be typically realized by preliminarily writing thepatterns corresponding to α₁, α₂, . . . , α₆ in 6×3 bit memory means oneafter another and successively reading out them from the latter formultiplication.

Alternatively, α₁, α₂, . . . , α₆ may be generated by a down countercircuit formed of a 3 bit binary counter. This is because it is onlynecessary to successively generate 3 bit patterns which are differentfrom one another.

The patterns thus generated are successively applied to themultiplication circuit 140. In the example illustrated, themultiplication circuit 140 is formed of a 2⁶ ×3 bit ROM device includingsix inputs and supplied with input patterns α_(i) and a_(i) respectivelyand three outputs from which an output a_(i) α_(i) is delivered as shownon the upper portion of FIG. 14. In the ROM device the input patternsa_(i) and α_(i) are regarded as addresses and output patternscorresponding thereto are preliminarily written. For example, if a_(i)is expressed by (010), or if α_(i) is of (011) corresponding to α³ thenan associated output pattern is expressed by a_(i) α_(i) =αα³ =α⁴. FromFIG. 13 it is seen that a corresponding output pattern is expressed by(110). Accordingly, three bits indicating a_(i) along with three bitsindicating α_(i) define respective addresses and the contents of theaddresses may be selectively read out as the products of a_(i) andα_(i). FIG. 14 also shows on the lower portion thereof a tableillustrating addresses (α_(i), a_(i)) and the corresponding ROMcontents.

From the foregoing it will readily be understood that a division circuitas will be described later may be similarly formed as the multiplicationcircuit 140.

Then, 3 bit products a_(i) α_(i) from the multiplication circuit 140 areapplied via the three EXCLUSIVE OR gates 142 to the memory circuit 144where a continued addition is effected as in the memory circuit 134.After the addition has been effected six times in the memory circuit144, a pattern corresponding to a₇ is registered in the shift register146 operated in the same manner as the shift register 136. Then the a₇pattern registered in the shift register 146 passes through thatselector 154 connected to the output of the shift register 146 and isdeveloped at an associated one of the output terminals 156.

On the other hand ##EQU4## registered in the shift register 136 and thea₇ pattern or value registered in the shift register 146 are applied tothe EXCLUSIVE OR gate 148 where they are added to each other in one bitcorrespondence to form a 3 bit a₈ pattern. This 3 bit a₈ pattern issupplied to that selector 154 connected to the output of the EXCLUSIVEOR gate 148 and then developed at an associated one of the outputterminals 156.

Thus 6×3 bit data groups a₁, a₂, a₃, a₄, a₅ and a₆ are added with checksymbols a₇ and a₈.

The process as described above is repeated 50 times following the timingpulses or signals ET23 shown in FIG. 12.

Each of the C₁ encoders 152 connected to the respective input terminals150 generates 16 check bits with respect to the 150 bit informationgroup arranged in the associated row of the rectangular array. Also, theC₁ encoder 152 connected to the output of the shift register 146generates 16 check bits by regarding the 50 check symbols a₇ from the C₂encoder as a 150 bit data group. Similarly, the C₁ encoder 152 connectedto the output of the EXCLUSIVE OR gate 148 generates 16 check bits byregarding the 50 check symbols a₈ from the C₂ encoder as a 150 bit datagroup.

After each of the selectors 154 has delivered a 150 bit data group tothe mating output terminal 154 under the control of the pulses EG12 (seeFIG. 12) the same is applied with the pulses EG13 (see FIG. 12) but notwith the pulses EG12 to deliver the associated 16 check bits to themating output terminal 156.

A codeword of 8×166 bits thus formed is entered into the synchronizingpattern addition circuits 26 (see FIG. 6A) through the output terminals156. In the synchronizing pattern addition circuits 26, a synchronizingpattern in the form of a rectangular array and including 8×12 bits isadded to each codeword to form a rectangular array of 8×178 bits.

The 8×178 bit rectangular array is passed through the modulationcircuits 28 and is then recorded on the magnetic tape 32 by therecording heads 30 as shown in FIG. 6A.

DETAILS OF DECODING UNIT

Then as shown in FIG. 6B, the 8×178 bit rectangular array or the signalrecorded on the magnetic tape 32 is reproduced by the reproducing heads34 and successively processed by the demodulation circuits 36, thesynchronizing pattern detection circuits 38 and the TBC circuits 40. Asa result, a received word, including 8×166 bits, is reproduced. Thereceived word corresponds to a codeword of a G.P. code and enters theC_(Z) decoder 42.

FIG. 15 shows the details of the C₁ decoders 44 included in the C_(Z)decoder 42. In the arrangement illustrated, a set of input terminals160, in this case, eight terminals adapted to be connected to the T.B.C.circuits 40 respectively, are connected to respective C₁ decoders 162,labelled "CRC" and also to respective shift registers 164, each registerincluding 150 bit positions and forming a delay circuit controlled withpulses DT13. Each of the C₁ decoders includes a reset input R havingreset pulses DT18 applied thereto, a clock input CLK having clock pulsesDT15 applied thereto, and an output connected to a different one ofeight output terminals 166. Those output terminals 166 are connected tothe erasure weight and location calculation circuits 50 and 52respectively (see FIG. 6B). The shift registers 164 outputs areconnected to respective output terminals 168 adapted to be connected tothe received word forming circuit 54 for codes C₂ (see FIG. 6B).

The received word with 166 bits corresponding to the codeword of thecode C₁ is applied to the each of the input terminals 160 and thenentered into the associated C₁ decoder 162 which detects if an erroroccurs in the codeword. When the codeword is erroneous, as determinedthereby, the associated C₁ decoder 162 delivers a binary ONE to themating output terminal 166 of the erasure weight and location circuits.Otherwise, it delivers a binary ZERO to that output terminal 166.

Simultaneously with the error detection effected by the C₁ decoders 162,150 bit data groups are supplied to each of the output terminals 168through the mating delay circuit 164. The delay circuit 164 includes 150bit positions and is operative to delay data applied by one codeword ofa G.P. code until the associated C₁ decoder 162 has been completed toeffect the error detection. This is because information concerning thedetected error is utilized as an erasure upon the decoding by the C₂decoder.

FIG. 16 shows the details of the received word-of-code C₂ formingcircuit 54. In the arrangement illustrated, output terminals 168 areadapted to be connected to the received word-forming circuit 54_(A) ofcode C₂ whose details are shown in FIG. 16.

A set of input terminals 170 is adapted to be connected to the outputterminals 168 of the shift registers 164 respectively. Each of the inputterminals 170 is connected to a first delay circuit 172 subsequentlyconnected to a second delay circuit 174 which is, in turn, connected toa third delay circuit 176. Each of the delay circuits 172, 174 or 176 isformed of a D FLIP-FLOP including a clock input CLK having clock pulsesDT13 applied thereto and imparting a time delay corresponding to one bitof an input applied thereto.

All the first delay circuits 172, are connected to a first set of outputterminals 178, respectively and the second delay circuits 174 areconnected to a second set of output terminals 180. Similarly, the thirddelay circuits 176 are connected to a third set of output terminal 182.In this case, each set of terminals includes eight output terminals andis connected to selectors connected to different ones of selectorsdisposed in the C₂ decoder 56 (see FIG. 6B).

Data is applied to the input terminals 170 in an incremental manner byone bit by means of the serially connected delay circuits 172, 174 and176. Therefore, the eight bits developed at the eight output terminals182 comprise data temporarily preceding those developed at the eightoutput terminals 180 by one bit and the eight bits developed at theoutput terminals 180 comprise data temporarily preceding those developedat the output terminals 178 by one bit.

From the foregoing, it is seen that data transmitted along eightchannels are partitioned into groups, each including three bits, to formthe received words of the code C₂, each arranged in a rectangular arrayincluding 8×3 bits. The received words of the code C₂ thus formed aresuccessively delivered to the C₂ decoder 56.

In the erasure weight and location calculation circuits shown in FIG.17, error detected data from the C₁ decoders 162 shown in FIG. 15 isapplied to a set of input terminals 190a, 190b, 190c, 190d, 190e, 190fand 190h. When any of the C₁ decoders 162 detects an error, a binary ONEis applied to an associated one of those input terminals. Otherwise,that input terminal receives a binary ZERO.

Those eight input terminals 190 are connected to both the erasure weightcalculation circuit designated here by the reference numeral 192 and theerasure location calculation circuit designated here by the referencenumeral 194. The erasure weight calculation circuit 192 is connected viafour leads 196-0, 196-1, 196-2 and 196-3 to a shift registor 198 whichis subsequently connected to four output terminals 200-0, 200-1, 200-2and 200-3. The shift register 198, including a set input having setpulses DT11 applied thereto is formed of D FLIP-FLOP's and operative toregister therein erasure weight information until one codeword of a G.P.code is decoded.

The erasure location calculation circuit 194 is connected via six leads202u, 202v, 202w, 202x, 202y and 202z to a shift register 204 which issimilar to the shift register 198. The shift register 204 is connectedto six output terminals 206u, 206v, 206w, 206x, 206y and 206z. The shiftregister 204 registers therein erasure location information until onecodeword of the G.P. code is decoded.

When no error is detected in any one of the rows of the rectangulararray or the tracks, or when no erroneous track is detected, a binaryONE is developed on the lead 196-0 and then at the output terminal200-0. When an error is detected on a single one of the tracks or when asingle erroneous track is detected, a binary ONE is developed on thelead 196-1 and then at the output terminal 200-1. Also, when errors aredetected on two tracks, or when two erroneous tracks are detected, abinary ONE is developed on the lead 196-2 and then at the outputterminal 200-2. Similarly when errors are detected on not less than twotracks or when not less than two erroneous tracks are detected, a binaryONE is developed on the lead 196-3 and then at the output terminal200-3.

Error location information α_(i) is developed on the leads 202u, 202vand 202w and then at the output terminals 206u, 206v and 206w whileerror location information α_(j) is developed on the leads 202x, 202yand 202z and then at the output terminals 206x, 206y and 206z where iand j are integers and where 1≦i<j≦8. Each of i and j designates aserial number of the eight tracks and is in the form of a binary numberincluding three bits. In the example illustrated, each of the i and jmay be a binary number of (111), (110), (101), (100), (011), (010),(001) or (000) identifying the first, second, third, fourth, fifth,sixth, seventh or eighth track respectively, as will be seen in thefirst row of the righthand side of the expression (6).

When no erroneous track is detected, each of α_(i) and α_(j) is a binaryZERO which is developed on each set of the output terminals 206u, 206v,206w and 206x, 206y, 206z. When a single erroneous track is detected,α_(i) indicates that track having an error detected while α_(j) isalways of binary ZERO. When two erroneous tracks are detected, α_(i)designates that track including the error and having the smaller serialnumber while α_(j) designates that track having the larger serial numberand including the error. However when more than two erroneous tracks aredetected, the values of α_(i) and α_(j) are not defined.

The erasure weight calculation circuit 192 may be formed of a parallelin-serial out 8 bit shift register, three 3 bit binary counters and acounter decoding circuit. Alternatively, the circuit 192 may be formedof a 2⁸ ×4 bit ROM device. In the latter case, binary numbers, eachincluding four bits, are preliminarily written in the device so that thecontent stored at each of the addresses as determined by binary patternsapplied to the inputs to the device, determines which of the leads196-0, 196-1, 196-2 and 196-3 delivers an output, by the number ofbinary ONE's included in the content.

The erasure location calculation circuit 194 may be formed of a 2⁸ ×6bit ROM device having binary patterns applied to and delivered from thesame as shown, by way of example, in FIG. 18. In the table illustrated,the lefthand column as viewed in FIG. 18 includes 8 bit binary numbersapplied to the input terminals 190a through 190h (see FIG. 17). Thatcolumn is divided into eight sub-columns labelled a, b, c, d, e, f, gand h having disposed therein binary ZERO's or ONE's which are appliedto the input terminals 190 suffixed with the same reference charactersas the sub-columns.

An intermediate column designated by α_(j) is divided into threesub-columns x, y and z having arranged therein binary ZERO's and ONE'sdeveloped on the lead 202 suffixed with the same reference characters asthe sub-columns. Similarly, the righthand column α_(i) as viewed in FIG.18 illustrates binary outputs developed on the leads 202u, 202v and202w.

Furthermore, a first row labelled A shows the input and output patternsformed when no erroneous track is detected and the succeeding eightrows, labelled B, show the input and output patterns selectively formedwhen a single erroneous track is detected. The last twenty-eight rows,labelled C, show the input and output patterns selectively formed uponthe detection of two erroneous tracks.

In the ROM device it is necessary to deliver only two binary patterns,each including three bits, for each input pattern including eight bits.Therefore, the ROM device can be realized by having 6 bit contentspreliminarily wirtten thereinto at addresses defined by 8 bit inputpatterns.

Alternatively, the erasure location calculation circuit may be formed ofgate circuits so that, with respect to eight inputs a, b, c, d, e, f, gand h, logic expressions for outputs x, y, z, u, v and w are obtained byregarding the intact input and output patterns shown in FIG. 18 as thetruth table thereof.

Alternatively, the erasure location calculation circuit 194 may beformed of gate circuits. In this case, logic expressions for the outputx, y, z, u, v and w may be deduced as functions of the inputs a, b, c,d, e, f, g and h so as to hold the truth table expressed by the inputand output patterns shown in FIG. 18.

In the example illustrated, the erasure location calculation circuit 194is typically formed of six gate circuits as shown in FIG. 19. In thearrangement illustrated, the eight input terminals 190a through 190hshown in FIG. 17 are connected in a parallel circuit relationship to sixgate circuits 208x, 208y, 208z, 208u, 208v and 208w subsequentlyconnected to the leads 202x, 202y, 202z, 202u, 202v and 202w (see FIG.17) respectively.

It is assumed that a, b, c, d, e, f, g and h designate input signalsapplied to the input terminals 190a, 190b, 190c, 190d, 190e, 190f, 190gand 190h respectively and x, y, z, u, v and w designate output signalsdeveloped on the leads 202x, 202y, 202z, 202u, 202v and 202wrespectively.

It will readily be understood that the gate circuits 208x through 208wcan be constructed by following the logic expressions for deriving theoutput signals x, y, z, u, v and w from the input signals a, b, c, d, e,f, g and h respectively.

For example, the construction of the gate circuit 208x will now bedescribed. FIG. 18 illustrate six output patterns including the outputsignal x having a value of binary ONE. Therefore x may be expressed bythe logic expression: ##EQU5## where the symbol + designates the "OR"operation and ⊕ designates the "EXCLUSIVE OR" operation. It will readilybe understood that the expression (9) can be realized by AND, OR,EXCLUSIVE OR, and inverter gates connected as shown in FIG. 20 withoutput signals denoted beside the outputs of various gates.

The foregoing is equally applicable to the remaining gate circuits shownin FIG. 17.

The C₂ decoder 56 shown in FIG. 6 is of a circuit configuration asillustrated in FIGS. 21A and 21B. In the arrangement illustrated, threesets of input terminals 210, 212 and 214 are adapted to be connected tothe sets of the output terminals 178, 180 and 182 of the received wordforming circuit 54 for the code C₂ shown in FIG. 16 respectively. In theexample illustrated, each set includes eight output terminals. Also fourinput terminals 216-0, 216-1, 216-2 and 216-3 are adapted to receiverespective outputs from the output terminals 200-0, 200-1, 200-2 and200-3 of the erasure weight calculation circuit 192 (see FIG. 17). Aswill readily be understood from the description for FIG. 17, the inputterminals 216-0, 216-1, 216-2 and 216-3 have applied thereto dataconcerning the detection of no erroneous track, the detection of asingle erroneous track, the detection of two erroneous tracks and thedetection of not less than three erroneous tracks respectively.

Further each of two input terminals 218i or 218j is adapted to beconnected to the three output terminals 206u, 206v and 206w or 206x,206y and 206z of the erasure location calculation circuit 194 (see FIG.17). Therefore, the input terminals 218 are representative of threeinput terminals adapted to be connected to those three output terminalsof the erasure location circuit 194. Therefore, the erroneous locationdata α_(i) or α_(j), including three bits, is developed in a parallelcircuit relationship at the input terminals 218i or 218j including thethree input terminals.

It is noted that a lead extending from the input terminal 218i or 218jincludes three parallel leads and is designated by the reference numeral3 above a slanted line crossing that lead. In the following descriptionfor FIGS. 21A and 21B, any lead with the abovementioned notationincludes three parallel leads which are, in turn, connected to a triadof logic elements arranged in a parallel circuit relationship and thetriad of logic elements are described as a single logic element unlessotherwise stated.

Three selectors 220, 222 and 224 are connected to the respective sets ofthe input terminal 210, 212 and 214 and select successively data appliedto the latter in the order of the first, second . . . and eighth tracksand in response to track selecting pulses EG21, EG22, . . . , and EG28successively applied to the selectors.

The selectors 220, 222 and 224 include respective outputs connected to adelay circuit 226 formed of three 6 bit shift registers arranged in aparallel circuit relationship and having bit positions having shiftingpulses DT24 applied thereto and also to one input of three EXCLUSIVE ORgates 228. Those gates 228 are connected to a memory device 230including three MASTER-SLAVE FLIP-FLOP's having reset and clock pulsesDT21 and DT22 applied to reset and clock inputs thereof. Each of theMASTER-SLAVE FLIP-FLOP's includes an output connected to the other inputof its associated EXCLUSIVE OR gate 228 and also to each of the three DFLIP-FLOP's forming a shift register 232 having clock pulses DT23applied to its clock input CLK and acting as a latch circuit. The shiftreigster 232 is connected to an output terminal 234 representing threeoutput terminals at which a 3 bit syndrome signal So is developed.

The outputs of the selectors 220, 222 and 224 are further connected to amultiplication circuit 236 having an α_(i) generator circuit 238connected thereto. The multiplication circuit 236 and the α_(i)generator circuit 238 are similar in construction and connected in thesame manner as described above in conjunction with the multiplicationcircuit 140 and the α_(i) generator circuit 138 shown in FIG. 11B.However, α_(i) generator circuit 238 has reset and clock pulses DT21 andDT22 applied to its reset and clock inputs R and CLK respectively. Theα_(i) generator circuit 238 ma be formed of a ROM device, in which 3 bitpatterns corresponding to the elements α₁, α₂, . . . , α₆, 1, 0 of theGalois field GF(2³) are preliminarily written and from which every threebits are successively read out in response to the clock pulses DT22.Alternatively, the α_(i) generator circuit 238 may be formed of a downcounter as described above.

The multiplication circuit 236 is operative over the Galois field GF(2³)to deliver three bits with respect to each 6 bit input pattern and maybe formed of a 2⁶ ×3 bit ROM device. The multiplication circuit 236 isconnected via EXCLUSIVE OR gates 240 and a memory device or a register242 to a shift register or a latching circuit 244 in the same manner asthe outputs of the selectors 220, 222 and 224 are connected to the shiftregister 232. The components 240, 242 and 244 are identical to thecomponents 228, 230 and 232 respectively excepting that the component244 or the shift register delivers a 3 bit syndrome signal S₁ to anoutput terminal 246 similar to the output terminal 234.

The output terminal 234 is connected to both a division circuit 248 anda multiplication circuit 250 to which the input terminal 218j isconnected. The multiplication circuit 250 may be identical to themultiplication circuit 236. The division circuit 248 executes a divisionexpressed by S₁ ÷S₀ over the Galois field GF(2³) and may be formed of a2⁶ ×3 bit ROM device into which the results of this division arepreliminarily written.

The S₀ α₁ multiplication circuit 250 is connected to one input of anEXCLUSIVE OR gate 252 whose other input is connected to the outputterminal 246 and which delivers an output (S₁ +α_(j) S₀) to anotherdivision circuit 253. The input terminals 218i and 218j are connected toa pair of inputs of an EXCLUSIVE OR gate 254 which delivers an output(α_(i) +α_(j)) to one input of an OR gate 256 whose other input isconnected to the output of an AND gate 258. The AND gate 258 has oneinput connected to the output of the division circuit 248 and the otherinput connected to the input terminal 216-0. The OR gate 256 has anoutput connected to one input of the division circuit 253 operative todivide the output (S₁ +α_(j) S₀) from the EXCLUSIVE OR gate 252 by theoutput (α_(j) +α_(i)) from the EXCLUSIVE OR gate 254 passed through theOR gate 256. The division circuit 253 may be formed of a 2⁶ ×3 bit ROMdevice and has an output connected to one input of an EXCLUSIVE OR gate259 whose other input is connected to the output terminal 234.

Each of the EXCLUSIVE OR gates 252, 254 or 259 executes the additionover the Galois field GF(2³) and includes three EXCLUSIVE OR gatesarranged so that each of two inputs is supplied with a different one ofthree parallel bits and one output delivers each of three parallel bits.

The OR gate 256 includes three OR gates arranged so that their two setsof inputs are supplied with two sets of three parallel bits respectivelyand a single output delivers a different one of three bits in parallel.

The output of the division circuit 248 is connected to one input of anAND gate 260 whose other input is connected to the input terminal 216-1.The input terminal 218i is connected to one input of an AND gate 262whose other input is connected to the input terminal 216-1. An AND gate264 has one input connected to one input of the AND gate 262 and theother input connected to the input terminal 216-2. An AND gate 266 hasone input connected to the output of the division circuit 248 and theother input connected to an output of an OR gate 268 whose inputs arerespectively connected to the input terminals 216-0 and 216-1.

The AND gates 260 and 262 are connected to a pair of inputs to acomparator 270 while the AND gates 264 and 266 are connected to theinputs of an OR gate 272. The output of the OR gate 268 is alsoconnected to an inverter 274.

The input terminal 218j is connected to one input of a comparator 275whose other input is connected to another α_(i) generator 282. Thecomparator 276 has an output connected to one input of an AND gate 278whose other input is connected to the output of the EXCLUSIVE OR gate259. The AND gate 278 has an output connected to one input of an ANDgate 280 whose other input is connected to the output of the inverter274.

The α_(i) generator circuit 282 is identical to the α_(i) generatorcircuit 238 excepting that its clock input CLK is supplied with clockpulses DT25 but not with the clock pulse DT22 and is connected to theother input of the comparator 276 and also to one input of a comparator284. The comparator 284 has its other input connected to the output ofthe OR gate 272 and has an output connected to one input of an AND gate286. The AND gate 286 has its other input connected to the output of thedivision circuit 254 and has an output connected to one input of an ANDgate 288 whose other input is connected to a coincidence output=of thecomparator 270.

Then, an EXCLUSIVE OR gate 290 has three inputs connected to the delaycircuit 226, outputs of the AND gates 280 and 288 respectively, and hasan output connected to an output terminal 292 for the C₂ decoder 56.

Each of the AND gates 258, 260, 262, 266, 278, 280, 286 and 288 includesthree AND gates arranged so that each of two inputs is supplied with adifferent one of three parallel bits and one output delivers each ofthree parallel bits.

The OR gate 272 is identical to the OR gate 256.

The EXCLUSIVE OR gate 290 includes three EXCLUSIVE OR gates arranged sothat each set of three inputs is supplied with three parallel bits inparallel and one output delivers each of the three parallel bits.

The input terminal 216-3 is connected to one input of an OR gate 294whose other input is connected to a non-coincidence input ≠ of thecomparator 270. The OR gate 294 has an output connected to a set input Sof a mode monitoring R-S FLIP-FLOP 296 having reset pulses DT18 suppliedto its reset input R. This FLIP-FLOP 296 has an output connected to anoutput terminal 298 for use as a compensation flag.

Each of the comparators 270, 276 and 284 includes three gates arrangedso that an output at the coincidence output ≠ is operative to turn threegates on and off. Therefore, the coincidence output=corresponds to threeleads extended.

It is noted that each of the division circuits 248 or 254 is set toproduce a null output with a division having a null value.

The C₂ decoder shown in FIG. 21 functions as a decoder for (8,6)Reed-Solomon codes over the Galois field GF(2³) as defined by the paritycheck matrix expressed by the expression (6). Such a decoder isoperative to decode each Reed-Solomon code in the process divided infour stages including (i) the calculation of syndrome signals S₀ and S₁,(ii) the calculation of error positions, (iii) the calculation of errorpatterns and (iv) the correction of the errors.

In the first stage of calculating the syndrome signals S₀ and S₁, thesyndrome signals S₀ and S₁ are first given by ##EQU6## where r₁, r₂, . .. , r₈ designate the symbols of the Galois field GF(2³) or receivedsymbols of the Reed-Solomon code or the code C₂. In other words, theyare formed of transmitted symbols a₁, a₂, . . . , a₈ added with theerror patterns e₁, e₂, . . . , e₈ respectively.

In the arrangement of FIG. 21A, the three selectors 220, 222 and 224successively pick up data delayed in incremental manner by one codewordof the G.P. code from the eight rows or track in the order of the first,second, . . . , eighth tracks in response to the track selecting pulsesEG21, EG22, . . . , EG28 successively applied thereto. The data pickedup at a time include three bits for each track. The three EXCLUSIVE ORgates 228 cooperate with the M-S FLIP-FLOP's forming the memory circuit230 to execute the addition following the expression. The resulting sumS₀ in the form of three parallel bits is supplied to the output terminal234 through the 3×6 bit shift register 232.

As described above, α_(i) preliminarily written into the α_(i) generatorcircuit 238 is successively read out by the multiplication circuit 236.The read 3 bit α_(i) 's and the 3 bit outputs r_(i) from the selectors220, 222 and 224 are successively applied to the multiplication circuit236 where r_(i) 's are successively multiplied by α_(i) 's. The memorycircuit 242 including M-S FLIP-FLOP's form an adder with the threeEXCLUSIVE OR gates 240 to perform the calculation following theexpression (11) by adding successively the products from themultiplication circuit 236 to each other. The resulting sum S₁ in theform of three parallel bits is delivered to the output terminal 246through the shift register 244.

The use of the Reed-Solomon code defined by the expression (6) permitsthe correction of the following cases:

(A) One erroneous track;

(B) The erasure of one track; and

(C) The erasure of two tracks.

The operation of the C₂ decoder as shown in FIGS. 21A and 21B will nowbe described in conjunction with errors or erasures differently causedon the tracks on the assumption that s designates the number of erasuresor an erasure weight and e designates the number of undected errors. Theabovementioned cases (A), (B) and (C) correspond to e=1 and s=0, e=0 ands=1, and e=0 and s=2 respectively.

For a better understanding of the operation of the C₂ decoder, theerasure of two tracks will first be described.

(i) Erasure of Two Tracks or e=0 and s=2.

It is assumed that errors have been caused on the i-th and j-th trackswhere i is smaller than j. Under the assumed conditions, the decoding ofthe code C₁ gives erasure location data i and j. Then, correspondingvalues of α_(i) and α_(j) are calculated. For example, after clockpulses have been supplied to a 3 bit down counter set to a binary numberor pattern (111) (i-1) and (j-1) times respectively, the down counterprovides the erasure location data α_(i) and α_(j) respectively.Alternatively, the data α_(i) and α_(j) may be read out from a ROMdevice in which there are stored binary numbers of α_(i) in the order ofthe elements located in the first row on the righthand side of theexpression (6) for the parity check matrix. In the latter case, thecontents at the i-th and j-th addresses provide the data α_(i) and α_(j)respectively.

Then, data e_(i) and e_(j) are derived from the syndrome signals S₀ andS₁ developed at the output terminals 234 and 246 following theexpressions

    S.sub.0 =e.sub.i +e.sub.j                                  (12)

and

    S.sub.1 =e.sub.i α.sub.i +e.sub.j α.sub.j      (13)

This results in

    e.sub.i =(α.sub.j S.sub.0 +S.sub.1)/(α.sub.i +α.sub.j) (14)

and

    e.sub.j =e.sub.i +S.sub.0                                  (15)

Signals for the e_(i) and e_(j) are formed in the arrangement of FIG. 21as follows: When two erroneous tracks are detected, a binary ONE entersthe input terminal 216-2 while the erasure position data α_(i) and α_(j)in the form of three parallel bits enter the input terminals 218i and218j respectively. Thus the multiplication circuit 250 forms the productα_(j) S₀ of S₀ from the output terminal 234 and the α_(j) from the inputterminal 218j. Then, the EXCLUSIVE OR gate 252 adds S₁ from the outputterminal 246 to α_(j) S₀ from the multiplication circuit 250 to form thesum S₁ +α_(j) S₀. Then, supplied to the division circuit 253 are theoutput (S₁ +α_(j) S₀) from the EXCLUSIVE OR gate 252 and an output(α_(i) +α_(j)) from the EXCLUSIVE OR gate 254 passed through the OR gate256. As a result, the division circuit 253 executes the division of (S₁+α_(j) S₀)/(α_(i) +α_(j)) and produces the e_(i) output in the form ofthree parallel bits.

On the other hand, the signal S₀ at the output terminal 234 is added tothe output e_(i) from the division circuit 254 by the EXCLUSIVE OR gate259. Accordingly, the e_(j) output is developed in the form of threeparallel bits at the output of the gate 259.

The erasure location data α_(i) entered into the input terminal 218ipasses through the gates 264 and 272 and then enters the comparator 284because the AND gate 264 is opened at that time by means of the binaryONE developed at the input terminal 216-2 as described above. The α_(j)developed at the input terminal 218j is also supplied to the comparator276. On the other hand, the α_(i) generator circuit 282 has supplied toits clock input CLK the shifting clock pulses DT25 to generatesuccessively symbols, each including three bits. Under thesecircumstances, the AND gate 286 is permitted to pass the output α_(i)from the comparator 284 therethrough for a symbol time interval forwhich the signal α_(i) from the input terminal 218i coincides with theoutput from the α_(i) generator circuit 282. As a result, the errorpattern e_(i) passed through the AND gate 286 is applied to theEXCLUSIVE OR gate 290 through the AND gate 288 and added to the outputfrom the shift register 226 in that gate 290 resulting in the correctionof the error e_(i). Under these circumstances, the AND gate 288 isalways put in its open state to permit the error pattern e_(i) to passtherethrough for the following reasons: Sincerely a binary ZERO ispresent at the input terminal 216-1, the AND gates 260 and 262 providenull outputs. Therefore, those null outputs are applied to thecomparator 270 which, in turn, determines that the two applied inputsare equal to each other. Thus the comparator 270 delivers an output fromits coincidence output=to the AND gate 288. Accordingly, the AND gate288 is put in its open state to permit the error pattern e_(i) to alwayspass therethrough.

In order to correct the error pattern e_(j), the latter is applied tothe other input of the AND gate 278 as described above. At that time,the AND gate 278 is put in its open state for a symbol time interval forwhich the signal α_(j) at the input terminal 218j coincides with theoutput from the α_(i) generator circuit 282 as determined by thecomparator 276. The EXCLUSIVE OR gate 290 similarly adds the errorpattern e_(j) passed through the AND gate 280 to the output from theshift register 226 resulting in the correction of the error patterne_(j). At that time, the error pattern e_(j) is permitted to passthrough the AND gate 280 because the latter is put in its open state bymeans of the OR gate 268 and the inverter 274 except that binary ONE'sare developed at the input terminals 216-0 and 216-1.

(ii) Non-Detection of One Erroeneous Track or s=0 and e=1.

Syndrome signals S₀ and S₁ may be expressed by

    S.sub.0 =e.sub.i                                           (16)

and

    S.sub.1 =e.sub.i α.sub.i                             (17)

respectively. Therefore, α_(i) =S₁ /S₀ indicates error locationinformation or data. At that time, both the erasure weight and locationcalculation circuits 192 and 194 respectively do not provide dataconcerning the erasure. That is, s has a null value. Under thesecircumstances, the division circuit 248 calculates the α_(i). Althoughthe α_(i) is of a pattern of S₀, it is possible to correct thenon-detection of one erroneous track by utilizing one portion of thecircuit for correcting the erasure of two tracks as described above.

More specifically, the output of S₁ +α_(i) S₀ from the EXCLUSIVE OR gate252 has only the value of S₁ because α_(i) has a null value. Only whenno erroneous track is detected, a binary ONE is developed at the inputterminal 216-0 and applied to the AND gate 258. Therefore, the output S₁/S₀ or α_(i) from the division circuit 248 passes through the AND gate258 and then enters the division circuit 253 through the OR gate 256.The division circuit 253 divides S₁ by α_(i) and produces the resultingquotient or output e_(i) as seen from the expression (17).

On the other hand, the erasure location data passes through the AND gate266 and then through the OR gate 272 until it is applied to thecomparator 284. Subsequently, the signal α_(i) passes through the ANDgate 286 which is put in its open state for a symbol time interval forwhich the signal α_(i) coincides with the output from the α_(i)generator circuit 282. Then, the EXCLUSIVE OR gate 290 executes theaddition of α_(i) to the output from the shift register 226, resultingin the correction.

Under these circumstances, the OR gate 268 and the inverter 274 areoperated to put the AND gate 280 in its closed state to prevent theother error pattern e_(j) from entering the EXCLUSIVE OR gate 290. Thisensures the right correction.

(iii) Erasure of One Track or s=1 and e=0.

The erasure weight and location calculation circuits 192 and 194 providepieces of information indicating the detection of one erroneous track.Under these circumstances, a binary ONE is developed at the inputterminal 216-1 and the signal α_(i) is developed at the input terminal218i. At that time, it is assumed that the signal α_(j) in the form ofall three bits of binary ZERO's is applied to the input terminal 218j.The signal α_(j), including all bits of binary ZERO's, indicates theeighth track as will readily be understood from the parity check matrixrepresented by the expression (6).

Then, the comparator 270 determines if the signal α_(i) at the inputterminal 218i or the value of α_(i) based on erasure informationcoincides with the output from the division circuit 248 calculated fromthe syndrome signals S₀ and S₁ alone. When determined so, the comparator270 delivers a binary ONE at the coincidence output=thereof. This causesthe AND gate 288 to be put in its open state. Therefore, the correctionis effected in the process as described above in conjunction with (ii)Non-Detection of One Erroneous Track.

(iv) Detection of One Erroneous Track and Erasure of One Track or s=1and e=1.

Each of the erasures weight and location calculation circuits 192 or 194produces only a single piece of erasure information. Assuming that adetected error has caused on the i-th track, the syndrome signals S₀ andS₁ may be expressed by

    S.sub.0 =e.sub.i +e.sub.i'                                 (18)

and

    S.sub.1 =e.sub.i α.sub.i +e.sub.i'α.sub.i'     (19)

respectively. Therefore, the output S₁ /S₀ from the division circuit 248may be expressed by

    S.sub.1 /S.sub.0 =(e.sub.i α.sub.i +e.sub.i'α.sub.i')/(e.sub.i +e.sub.i').                                               (20)

On the other hand, the signal α_(i) developed at the input terminal 218adue to the erasure location calculation circuit 194 does not generallycoincide in value with the S₁ /S₀ appearing in the expression (20) or atthe output from the division circuit 248. Thus, a non-coincidence isdetermined by the comparator 270. As a result, the comparator 270delivers a binary ONE at the non-coincidence output ≠ thereof whiledelivering a binary ZERO at the coincidence output=. This binary ZERO,which is supplied the AND gate 288, puts the latter in its closed stateto thereby prevent the correction. At the same time, the binary ONE isapplied via the OR gate 294 to the set input S of the R-S FLIP-FLOP 296which serves to change the normal correction mode to the compensationmode and vice versa.

In response to non-coincidence information originating from thecomparator 270, the R-S FLIP-FLOP 296 supplies a binary ONE to thecompensation flag output terminal 298 while holding this information fora decoding time interval required for a codeword of the particular G.P.code to be decoded. This decoding time interval is just long enough todecode a Reed-Solomon code which is a code C₂ 50 (which equals 150divided by 3) times.

Under these circumstances, the compensation circuit 62 (see FIG. 6) isenabled to apply data of that codeword of the G.P. code just precedingthat codeword including the error to the digital-to-analog converter 64(see FIG. 6).

The R-S FLIP-FLOP 296 is reset in response to a reset pulse DT18 appliedto its reset input R so as to apply a binary ZERO to the output terminal298. At that time, the normal correction is effected so that thecompensation circuit 62 is operated to supply to the digital-to-analogconverter 64 an unchanged output from the k₂ ×k₁ information matrixreproducing circuit 60.

(v) Detection of Errors on Not Less Than Three Tracks.

From the expression (4) it is seen that errors are caused whose numberexceeds the correction capability. At that time, a binary ONE from theinput terminal 216-3 is applied to the R-S FLIP-FLOP 296 through the ORgate 294. Therefore, the R-S FLIP-FLOP 296 supplies a binary ONE to theoutput terminal 298 whereby the compensation circuit 62 (see FIG. 6)corrects the errors in the manner as described above in conjunction withthe non-coincidence information from the comparator 270.

FIG. 22 is a timing chart illustrating timing signals applied to thearrangements shown in FIGS. 15, 16, 17 and 21A and 21B. In FIG. 22, DT11designates trains of block or frame timing pulses, each developed at apartition between one codeword of the G.P. code and an associatedsynchronizing pattern. DT12 designates a train of 12 timing pulses forwriting a synchronizing pattern following each frame pulse DT11. A trainof 150 timing pulses DT13 for writing information bits of a code C₁follows the train of pulses DT13 and is followed by a train of sixteentiming pulses for writing check bits for the code C₁, the last pulsebeing developed immediately before the next succeeding frame pulse DT14.DT15 designates a train of timing pulses for bits including 178 clockpulses for each frame. DT16 designates a train of 50 pulses forpartitioning bits running along an associated channel into three bitsapiece for purposes of calculation.

DT21 designates the train of timing pulses DT13 shown on an extendedtime base and having a pulse repetition period in which a train of eighttiming pulses DT22 is developed for executing calculation of bitsincluded in the eight tracks at bit intervals. DT23 is the train ofpulses DT16 shown on an extended time base and operative to transfer theresult of the abovementioned calculation at three bit intervals. DT24designates shifting pulses for the shift register 226. The shiftingpulses DT24 are shown as including 25 trains of pulses, each formed ofsix pulses developed in one pulse repetition period of the pulses DT11.Those pulses DT24 form timing pulses for successively supplyinginformation bits to the EXCLUSIVE OR gate 290 to correct error patterns.Further timing pulses DT25 are shown as including 50 pulse trains, eachformed of six pulses which serve to add the error pattern to the outputfrom the shift register 226 by means of the EXCLUSIVE OR gate 290.

Finally DG21, DG22, . . . , DG28 designate pulse trains of 150 trackpulses successively applied to the selectors 220, 222 and 224 in orderto successively pick up information bits from the eight tracks, one bitat an interval. The temporal relationship between each train of pulsesand the next succeeding trains of pulses is similar to that describedabove in conjunction with the trains of pulses EG21, EG22, . . . , EG26shown in FIG. 12.

FIG. 23 illustrates the details of a typical k₂ ×k₁ information matrixreproducing circuit shown at block 60 in FIG. 6B. The arrangementillustrates a set of input terminals 300k, 300j and 300i connected to aparallel in-serial out 3 bit shift register 302 controlled with theshifting pulses DT25 which is, in turn, connected to a first and asecond RAM device 304 and 306 respectively. Each of the RAM devices 305or 306 has a capacity of 6×150 bits and is selectively supplied withwrite pulses DT31 and read pulses DT41. Outputs of the first and secondRAM devices 304 and 306 are connected to an output selector 308subsequently connected to an output terminal 310.

The arrangement further includes another input terminal 312 havingapplied thereto a timing pulse indicating a partition between each pairof adjacent rectangular arrays, each array including 6×150 bits. Thattiming pulse is applied to T FLIP-FLOP 314 to be halved in pulserepetition frequency. The T FLIP-FLOP 314 output is connected to aninverter 316 which is in turn connected to a selector 318. The TFLIP-FLOP 314 output is also connected to the output selector 308 and toanother selector 320. The selectors 318 and 320 are connected to thefirst and second RAM devices 304 and 306 respectively and are operativeto alternately put the associated RAM devices in the write and readcycles of operation for each rectangular array of 6×150 bits under thecontrol of write and read address forming circuits 322 and 324respectively.

Each of the write and read address forming circuits 322 and 324respectively includes a counter and a counter decoding circuit thereinand are driven with timing pulses DT31 or DT41 to successively formwrite or read addresses respectively by counting the pulses DT31 or DT41with their associated counter. The write and read address formingcircuits 322 and 324 are connected to the selectors 318 and 320 throughoutput terminals 326 and 328 respectively.

The output selector 308 is adapted to be always connected to that RAMdevices put in the read cycle of operation. Therefore, the selector 308successively reads out data in the form of samples, each sampleincluding the original 15 bits from that RAM device operated in the readcycle. The data read out by the output selector 308 is successivelydelivered to the compensation circuit through the output terminal 310.

Data is written in that RAM device put in the write cycle of operationin the sequence shown in FIG. 24A. As shown, every three bits arewritten in first three columns of that RAM device in the order of first,second, third, fourth, fifth and sixth rows to form a first 6×3 bitrectangular array. Then, every three bits are written in the next threecolumns of the device in the same order to a second 6×3 rectangulararray of 6×3 bits. This writing process is executed with all the columnsof the RAM device to form 50 rectangular arrays of 6×3 bits arranged inthe column direction within the RAM device operated in the write cycle.

Data stored in each of the RAM devices 304 or 306 is read out from thatdevice put in the read mode of operation in the sequence shown in FIG.24B. The reading sequence is different from the writing sequence shownin FIG. 24A only in that in FIG. 24B every fifteen bits are read out asone sample.

FIG. 25 shows various trains of timing pulses as described above inconjunction with FIG. 23. In FIG. 25, a first row shows the train ofpulses DT25 described above in conjunction with FIG. 22 and a second rowshows the train of timing pulses DT30 which is a replica of the trainpulse DT25 but illustrated on an extended time base. A third row showsthe train of writing pulses DT31 including three pulses developed withinone pulse repetition period of the pulse train DT30. A fourth row showsdata written in the RAM device 304 and 304 under the control of thepulse trains DT31. More specifically, the input terminals 300k, 300j and300i successively receive data in the form of three parallel bits fromthe output terminal 292 (see FIG. 21). This data is applied to theshifter register 302 which delivers serially the data to that RAM deviceput in the write cycle of operation where the data is continuouslywritten into bit positions as determined by the write address formingcircuit 322 as shown in the fourth row labelled WRITE DATA where thereference numerals 1 through 6 in the circle designate row numbers andreference numerals 1, 2 and 3 designate the bit positions located ineach row of the device.

A pulse train DT11 shown in a fifth row is identical to the pulse trainof block timing signals DT11 illustrated in FIG. 22, and the pulse trainDT40 is shown under the pulse train DT11 as including 60 pulses withinone pulse repetition period of the pulse train DT11. The pulse trainDT40 is also applied, as a conversion signal, to the digital-to-analogconverter 64 (see FIG. 6B) connected to the output terminal 310 of thek₂ ×k₁ matrix reproducing circuit shown in FIG. 23. A seventh row showsa pulse train DT41, including 15 read pulses DT41, developed within onepulse repetition period of the pulses DT40. The lowermost low labelledREAD DATA shows data read out from that RAM device put in the read cycleof operation. The reference numerals 1, 2, . . . in the circlesdesignate successive samples, each sample including fifteen bitsdesignated by the reference numerals 1, through 15.

Referring back to FIG. 23, the T FLIP-FLOP 314 and the inverter 316 areoperated to put one of the RAM devices 304 or 306 in the read cycle ofoperation and to successively deliver every fifteen bits to the outputterminal 310 through the output selector 308, as shown in the lowermostrow in FIG. 25, at that time when the other RAM device is operated inthe write cycle.

Therefore, the RAM devices 304 and 306 are alternately operated in thewrite and read modes for each rectangular array of 6×150 bits, while theoutput selector 308 alternately reads data out from the two RAM devicesresulting in the continuous delivery of data to the output terminal 310(see FIG. 23).

It is to be understood that, if a quotient k₁ /f designating theparameter for codes C₂ is not an integer, then the k₁ bits may besuffixed with dummy bits so as to render the sum of k₁ and the number ofthe dummy bits equal to b multiplied by an integer.

While the present invention has been illustrated in conjunction with asingle preferred embodiment thereof, it is to be understood thatnumerous changes and modifications may be resorted to without departingfrom the spirit and scope of the present invention. For example, thearrangement shown in FIGS. 17, 21 and 23 has been described inconjunction with the code C₁ used as a error detecting code, but it isto be understood that the present invention is equally applicable to thecode C₁ used as either an error correction code or both an errorcorrection and an error detecting code. With the code C₁ used as theerror correction code, the erasure weight and location calculationcircuits are not required.

With the code C₁ used as the error correction code, the arrangement ofFIG. 21 is operated as follows: The input terminals 210, 212 and 214have entered thereinto a codeward of code C₁ after the correction oferrors. However, those input terminals may receive a code C₁ erroneouslycorrected but not rightly as it remains intact. In the latter case, itis assumed that such a code C₁ is corrected upon decoding an associatedcode C₂.

Assuming that a binary ONE is applied to the input terminal 216-O whilea binary ZERO is applied to each of the input terminals 216-1, 216-2,216-3, 218i and 218j, the arrangement of FIG. 21 can be used forcorrection purposes.

With a code C₁ used for the purposes of detecting and correcting errors,the received C₂ word forming circuit shown in FIG. 16, the erasureweight and location calculation circuits shown in FIG. 17, the C₂decoder shown in FIG. 21 etc. may be used in the same manner as they areused with the code C₁ for the purpose of detecting errors only. Morespecifically, the received C₂ word forming circuit 54 (see FIG. 6B)delivers to the C₂ decoder 56 (see FIG. 6B) information bits after thecorrection of errors. At that time, the C₂ decoder 56 may receiveinformation bits corrected erroneously.

It is here assumed that, when the codes C₁ have been decoded, the samecorrect s erasures in the horizontal direction and erroneously correctede errors caused in the correction or non-detection of e errors in thehorizontal direction. Under the assumed conditions, the C₂ decoder 56can correct s erasures and e errors corrected erroneously or undetectedin the same manner as described above in conjunction with the code C₂used only for error detecting purposes as long as the expression (4)holds.

The foregoing is equally applicable to the correction of error patternsother than those shown in FIG. 1, for example, one-dimensional randomerrors, one-dimensional burst errors, two-dimensional random errors andtwo-dimensional burst errors.

Also the present invention has been described in conjunction with abinary code but it is to be understood that the same is equallyapplicable to q-dimension codes where q is a prime number. Further whilethe present invention has been described in conjunction with rectangulararrays of bits having the parameters whose numbers are specified, it isto be understood that present invention is not restricted to apply tosystems having rectangular arrays of bits.

Further while the present invention has been illustrated and describedin conjunction with a plurality of C₁ encoders, it is to be understoodthat a single C₁ encoder may be used to encode every k₁ bits into everyn₁ bits, this encoding being repeated n₂ times. This is true in the caseof a plurality of C₁ decoders.

What we claim is:
 1. An encoding and decoding system for digitalinformation having a rectangular array of bits including k₁ bits in afirst direction and k₂ bits in a second direction orthogonal to thefirst direction which system comprises encoding means including anencoding adapting circuit for codes C₂ for dividing the k₁ bits in thefirst direction into b bits apiece, and forming a plurality of k₂ ×b bitrectangular arrays each including the b bits in the first direction andthe k₂ bits in the second direction, a C₂ encoder for encoding theplurality of k₂ ×b bit rectangular arrays into a plurality of n₂ ×b bitrectangular arrays each including the b bits in the first direction andn₂ bits in the second direction, a C₁ encoder for encoding the k₁ bitsin the first direction into n₁ bits by adding n₁ -k₁ check bits to thek₁ bits in the first direction, and a timing generator circuit forgenerating timing signals for controlling the operation of said encodingmeans to thereby encode the digital information into a codeword of ageneralized product code including the n₁ bits in the first directionand the n₂ bits in the second direction; and decoding means operativelyconnected to said encoding means by a transmission means for decodingthe digital information encoded by the encoding means; wherein said C₁and C₂ encoders are operative to encode in response to said timingsignals of said timing generator and wherein either said C₁ encoder orsaid C₂ encoder provides said generalized product code.
 2. An encodingand decoding system for digital information as claimed in claim 1,wherein the encoding means further includes an information matrixforming circuit for forming digital information not originally arrangedin a rectangular array of bits into a rectangular array of bitsincluding k₁ and k₂ bits in the first and second directionsrespectively; wherein said information matrix forming circuit and saidC₁ and C₂ encoders are operatively connected together and wherein saiddigital information from said information matrix forming circuit isencoded by either said C₁ or C₂ encoders.
 3. An encoding and decodingsystem for digital information as claimed in claim 2, wherein theinformation matrix forming circuit includes a pair of RAM devices,selector means connected to the pair of RAM devices to alternately placesaid RAM devices in their write and read cycles of operation and anotherselector means connected to the pair of RAM devices to read out datafrom the RAM device operated in its read cycle.
 4. An encoding anddecoding system for digital information as claimed in claim 1, whereinthe encoding adapting circuit for the code C₂ comprises delay circuits.5. An encoding and decoding system as claimed in claim 4, wherein theencoding adapting circuit for the code C₂ includes a plurality of seriescombinations of b 1-bit delay circuits one for each row in the firstdirection, each of the delay circuits delaying an input applied theretoby one bit.
 6. An encoding and decoding system for digital informationas claimed in claim 4, wherein the encoding adapting circuit for thecode C₂ includes RAM means and control circuit means for controllingaddresses in the RAM means.
 7. An encoding and decoding system fordigital information as claimed in claim 1, wherein the decoding means isdisposed on the receiver side to receive a codeword of a generalizedproduct code in the form of the rectangular array including the n₁ andn₂ bits in the first and second directions respectively through aselected one of a group of channels and a record medium and wherein thedecoding means includes a plurality of C₁ decoders one for every k₂ bitsin the second direction for decoding the k₁ bits in the first directionfrom the n₁ bits in the first direction, a received word-of-code C₂forming circuit for dividing an outputs from the C₁ decoders into b bitsapiece and forming a plurality of rectangular arrays including b bits inthe first direction and n₂ bits in the second direction, and a C₂decoder for decoding the rectangular arrays of k₂ ×b bits from therectangular arrays of n₂ ×b bits.
 8. An encoding and decoding system fordigital information as claimed in claim 7, wherein the receivedwork-of-code C₂ forming circuit includes a plurality of seriescombinations of b 1-bit delay circuits one for each row in the seconddirection, each of the delay circuits delaying an input applied theretoby one bit.
 9. An encoding and decoding system for digital informationas claimed in claim 7, wherein the received word-of-code C₂ formingcircuit includes RAM means and control circuit means for controllingaddresses in the RAM means.
 10. An encoding and decoding system fordigital information having a rectangular array of bits including k₁ bitsin a first direction and k₂ bits in a second direction orthogonal to thefirst direction which system comprises encoding means including anencoding adapting circuit for codes C₂ for dividing the k₁ bits in thefirst direction into b bits apiece, and for forming a plurality of k₂ ×bbit rectangular arrays each including the b bits in the first directionand the k₂ bits in the second direction, a C₂ encoder for encoding theplurality of k₂ ×b bit rectangular arrays into a plurality n₂ ×b bitrectangular arrays each including the b bits in the first direction andn₂ bits in the second direction, a C₁ encoder for encoding the k₁ bitsin the first direction into n₁ bits by adding n₁ -k₁ check bits to thek₁ bits in the first direction, and a timing generator circuit forgenerating timing signals for controlling the operation of said encodingmeans to thereby encode the digital information into a codeword of ageneralized product code including the n₁ bits in the first directionand the n₂ bits in the second direction; and decoding means operativelyconnected to said encoding means by a transmission means for decodingthe digital information encoded by the encoding means;wherein said C₁and C₂ encoders are operative to encode in response to said timingsignals of said timing generator and wherein either said C₁ encoder orC₂ encoder provides said generalized product code of said encodingmeans; wherein the encoding means further includes an information matrixforming circuit for forming digital information not originally arrangedin a rectangular array of bits into a rectangular array of bitsincluding the k₁ and k₂ bits in the first and second directionsrespectively; wherein the decoding means is disposed on the receiverside to receive a codeword of a generalized product code in the form ofthe rectangular array including the n₁ and n₂ bits in the first andsecond directions respectively through a selected one of a group ofchannels and a record medium and wherein the decoding means includes aplurality of C₁ decoders one for every k₂ bits in the first directionfor decoding the k₁ bits in the first direction from the n₁ in the firstdirection, a received word-of-code C₂ forming circuit for dividing anoutputs from the C₁ decoders into b bits apeice and forming a pluralityof rectangular arrays including b bits in the first direction and n₂bits in the second direction, and a C₂ decoder for decoding therectangular arrays of k₂ ×b bits from the rectangular arrays of n₂ ×bbits; wherein the decoding means further includes an information matrixreproducing circuit for reproducing the rectangular array including thek₁ and k₂ bits in the first and second directions respectively from anoutput from the C₂ decoder.
 11. An encoding and decoding system fordigital information as claimed in claim 1 wherein the decoding meansfurther includes an erasure weight calculation circuit and an erasurelocation calculation circuit for producing respectively erasure weightinformation and erasure location information indicating errors detectedin codes C₁ and means for correcting codes C₂ by utilizing the erasureweight information and erasure location information obtained fromdecoding code C₁.
 12. An encoding and decoding system for digitalinformation having a rectangular array of bits including k₁ bits in afirst direction and k₂ bits in a second direction orthogonal to thefirst direction which system comprises encoding means including anencoding adapting circuit for codes C₂ for dividing the k₁ bits in thefirst direction into b bits apiece, and forming a plurality of k₂ ×b bitrectangular arrays each including the b bits in the first direction andthe k₂ bits in the second direction, a C₂ encoder for encoding the k₁bits in the first direction into n₁ bits by adding n₁ -k₁ check bits tothe k₁ bits in the first direction, and a timing generator circuit forgenerating timing signals for controlling the operation of said encodingmeans to thereby encode the digital information into a codeword of ageneralized product code including the n₁ bits in the first directionand the n₂ bits in the second direction; and decoding means operativelyconnected to said encoding means by a transmission means for decodingthe digital information encoded by the encoding means;wherein said C₁and C₂ encoders are operative to encode in response to said timingsignals of said timing generator and wherein either said C₁ encoder orC₂ encoder provides said generalized product code of said encodingmeans; wherein the encoding means further includes an information matrixforming circuit for forming digital information not originally arrangedin a rectangular array of bits into a rectangular array of bitsincluding the k₁ and k₂ bits in the first and second directionsrespectively; wherein the decoding means is disposed on the receiverside to receive a codeword of a generalized product code in the form ofthe rectangular array including the n₁ and n₂ bits in the first andsecond directions respectively through a selected one of a group ofchannels and a record medium and wherein the decoding means includes aplurality of C₁ decoders one for every k₂ bits in the first directionfor decoding the k₁ bits in the first direction from the n₁ bits in thefirst direction, a received word-of-code C₂ forming circuit for dividingan outputs from the C₁ decoders into b bits apiece and forming aplurality of rectangular arrays including b bits in the first directionand n₂ bits in the second direction, and a C₂ decoder for decoding therectangular arrays of k₂ ×b bits from the rectangular arrays of n₂ ×bbits; wherein the decoding means further includes an erasure weightcalculation circuit and an erasure location calculation circuit forproducing respectively erasure weight information and erasure locationinformation indicating errors detected in codes C₁ and means forcorrecting codes C₂ by utilizing the erasure weight information anderasure location information obtained from decoding the code of C₁. 13.An encoding and decoding system for digital information as claimed inclaims 11 or 12, wherein the erasure weight calculation circuit includesan n₂ bit parallel in-serial out shift register, a b bit binary counterand a counter decoder circuit and the erasure location calculationcircuit comprises an ROM device including addresses determining inputpatterns applied thereto and output patterns preliminarily stored at theaddresses.
 14. An encoding and decoding system for digital informationas claimed in claims 11 or 12 wherein the erasure weight calculationcircuit comprises an ROM device including addresses determining inputpatterns applied thereto and output patterns preliminarily stored at theaddresses and the erasure location calculation circuit comprises an ROMdevice including addresses determining input patterns applied theretoand output patterns preliminarily stored at the addresses.